---------- Begin Simulation Statistics ---------- sim_seconds 0.057148 # Number of seconds simulated sim_ticks 57147901500 # Number of ticks simulated final_tick 57147901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 198372 # Simulator instruction rate (inst/s) host_op_rate 253689 # Simulator op (including micro ops) rate (op/s) host_tick_rate 159860838 # Simulator tick rate (ticks/s) host_mem_usage 323444 # Number of bytes of host memory used host_seconds 357.49 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 324160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7923136 # Number of bytes read from this memory system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 324160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 324160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 5065 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123799 # Number of read requests responded to by this memory system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 5672299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 138642641 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 144314940 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 5672299 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 5672299 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 94015701 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 94015701 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 94015701 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 5672299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 138642641 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 238330641 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128864 # Number of read requests accepted system.physmem.writeReqs 83950 # Number of write requests accepted system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue system.physmem.bytesWritten 5370816 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8158 # Per bank write bursts system.physmem.perBankRdBursts::1 8375 # Per bank write bursts system.physmem.perBankRdBursts::2 8229 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts system.physmem.perBankRdBursts::4 8317 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8089 # Per bank write bursts system.physmem.perBankRdBursts::7 7970 # Per bank write bursts system.physmem.perBankRdBursts::8 8070 # Per bank write bursts system.physmem.perBankRdBursts::9 7639 # Per bank write bursts system.physmem.perBankRdBursts::10 7818 # Per bank write bursts system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7882 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7978 # Per bank write bursts system.physmem.perBankRdBursts::15 8005 # Per bank write bursts system.physmem.perBankWrBursts::0 5181 # Per bank write bursts system.physmem.perBankWrBursts::1 5374 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts system.physmem.perBankWrBursts::6 5197 # Per bank write bursts system.physmem.perBankWrBursts::7 5049 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts system.physmem.perBankWrBursts::9 5087 # Per bank write bursts system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 57147867000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 128864 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83950 # Write request sizes (log2) system.physmem.rdQLenPdf::0 116734 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5176 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5178 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5197 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5188 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5385 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5293 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5718 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5316 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 38410 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 354.471023 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 215.710692 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 335.512328 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12078 31.44% 31.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 8121 21.14% 52.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4196 10.92% 63.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2833 7.38% 70.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2487 6.47% 77.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1687 4.39% 81.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1308 3.41% 85.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1147 2.99% 88.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4553 11.85% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 38410 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 24.969750 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 360.703721 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5155 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.272833 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.256213 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.766988 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 4532 87.88% 87.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 8 0.16% 88.04% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 487 9.44% 97.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 109 2.11% 99.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 13 0.25% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 4 0.08% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 3 0.06% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads system.physmem.totQLat 1657207000 # Total ticks spent queuing system.physmem.totMemAccLat 4073313250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers system.physmem.avgQLat 12860.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 31610.62 # Average memory access latency per DRAM burst system.physmem.avgRdBW 144.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 93.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 144.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 94.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.86 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing system.physmem.readRowHits 112198 # Number of row buffer hits during reads system.physmem.writeRowHits 62160 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes system.physmem.avgGap 268534.34 # Average gap between requests system.physmem.pageHitRate 81.93 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 150580080 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 82161750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 512592600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 11751586830 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 23977725000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 40479283620 # Total energy per rank (pJ) system.physmem_0.averagePower 708.378781 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 39762160500 # Time in different power states system.physmem_0.memoryStateTime::REF 1908140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15473270000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 139769280 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 76263000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 492016200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 11244014370 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 24422958750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 40378823040 # Total energy per rank (pJ) system.physmem_1.averagePower 706.620851 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 40500942500 # Time in different power states system.physmem_1.memoryStateTime::REF 1908140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14734649500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 14823153 # Number of BP lookups system.cpu.branchPred.condPredicted 9921447 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 393425 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 9508830 # Number of BTB lookups system.cpu.branchPred.BTBHits 6745421 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 70.938496 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1716328 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 114295803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed system.cpu.discardedOps 1165738 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.611727 # CPI: cycles per instruction system.cpu.ipc 0.620453 # IPC: instructions per cycle system.cpu.tickCycles 95732462 # Number of cycles that the object actually ticked system.cpu.idleCycles 18563341 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 156421 # number of replacements system.cpu.dcache.tags.tagsinuse 4067.059654 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42628242 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160517 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 265.568395 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 829804250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4067.059654 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992934 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992934 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2909 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86023319 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86023319 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 22869697 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22869697 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642191 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642191 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 84516 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 84516 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 42511888 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 42511888 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 42596404 # number of overall hits system.cpu.dcache.overall_hits::total 42596404 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 51738 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 51738 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207710 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 207710 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 43711 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 43711 # number of SoftPFReq misses system.cpu.dcache.demand_misses::cpu.data 259448 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 259448 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 303159 # number of overall misses system.cpu.dcache.overall_misses::total 303159 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 1479377187 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 1479377187 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 16921529000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 16921529000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 18400906187 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 18400906187 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 18400906187 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 18400906187 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22921435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22921435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128227 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 128227 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 42771336 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42771336 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42899563 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42899563 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002257 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002257 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340888 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.340888 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007067 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007067 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 70923.291708 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 60697.212311 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128425 # number of writebacks system.cpu.dcache.writebacks::total 128425 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22255 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22255 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100680 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 100680 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 122935 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 122935 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 122935 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 122935 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29483 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29483 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24004 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 24004 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 136513 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 136513 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160517 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160517 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 559151063 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 559151063 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8446390250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8446390250 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1684744250 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1684744250 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9005541313 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9005541313 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10690285563 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10690285563 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187199 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187199 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42924 # number of replacements system.cpu.icache.tags.tagsinuse 1852.595671 # Cycle average of tags in use system.cpu.icache.tags.total_refs 24987535 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 44966 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 555.698417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1852.595671 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.904588 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.904588 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50109970 # Number of tag accesses system.cpu.icache.tags.data_accesses 50109970 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 24987535 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 24987535 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 24987535 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 24987535 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 24987535 # number of overall hits system.cpu.icache.overall_hits::total 24987535 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 44967 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 44967 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 44967 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 44967 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 44967 # number of overall misses system.cpu.icache.overall_misses::total 44967 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 940451988 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 940451988 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 940451988 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 940451988 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 940451988 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 940451988 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25032502 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25032502 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25032502 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 25032502 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 25032502 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25032502 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001796 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001796 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001796 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001796 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001796 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001796 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20914.270198 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 20914.270198 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20914.270198 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 20914.270198 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20914.270198 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 20914.270198 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44967 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 44967 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 44967 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 44967 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 44967 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 44967 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 871086012 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 871086012 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 871086012 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 871086012 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 871086012 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 871086012 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001796 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001796 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001796 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001796 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001796 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001796 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19371.672827 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19371.672827 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19371.672827 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 19371.672827 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19371.672827 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19371.672827 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95727 # number of replacements system.cpu.l2cache.tags.tagsinuse 29852.290925 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 99928 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126845 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.787796 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26729.758607 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1556.401717 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1566.130601 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.815727 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047498 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.047795 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.911020 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1811 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12771 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15840 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 576 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2905147 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2905147 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 39890 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31903 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 71793 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 128425 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128425 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 39890 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 76545 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 39890 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits system.cpu.l2cache.overall_hits::total 76545 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 5077 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 26661 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 102278 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102278 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 5077 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 123862 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 128939 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5077 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123862 # number of overall misses system.cpu.l2cache.overall_misses::total 128939 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 407245000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1855059250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2262304250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8289427250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8289427250 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 407245000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10144486500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10551731500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 407245000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10144486500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10551731500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 44967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53487 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 98454 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 128425 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128425 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107030 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107030 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 44967 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 160517 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 205484 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 44967 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 160517 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 205484 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.112905 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403537 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.270797 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955601 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955601 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.112905 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.771644 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.627489 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.112905 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.771644 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.627489 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80213.708883 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85946.036416 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 84854.440944 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81047.999081 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81047.999081 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80213.708883 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81901.523470 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 81835.065419 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80213.708883 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81901.523470 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 81835.065419 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks system.cpu.l2cache.writebacks::total 83950 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5066 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 26587 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102278 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102278 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 5066 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123799 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5066 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123799 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342787750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1580541000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923328750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7010820250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7010820250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342787750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8591361250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 8934149000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342787750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8591361250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 8934149000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402359 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270045 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955601 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955601 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.627129 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.627129 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67664.380182 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73441.801032 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72340.946703 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68546.708481 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68546.708481 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 98454 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 98453 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89933 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449459 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 539392 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2877824 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 21370112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 333909 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 333909 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 333909 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 295379500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 68407488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 268248937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadReq 26586 # Transaction distribution system.membus.trans_dist::ReadResp 26586 # Transaction distribution system.membus.trans_dist::Writeback 83950 # Transaction distribution system.membus.trans_dist::ReadExReq 102278 # Transaction distribution system.membus.trans_dist::ReadExResp 102278 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341678 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 341678 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620096 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13620096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 212814 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 212814 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 212814 # Request fanout histogram system.membus.reqLayer0.occupancy 578378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) system.membus.respLayer1.occupancy 680081000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ----------