---------- Begin Simulation Statistics ---------- sim_seconds 47.397611 # Number of seconds simulated sim_ticks 47397610926500 # Number of ticks simulated final_tick 47397610926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 110253 # Simulator instruction rate (inst/s) host_op_rate 129665 # Simulator op (including micro ops) rate (op/s) host_tick_rate 5829907242 # Simulator tick rate (ticks/s) host_mem_usage 703216 # Number of bytes of host memory used host_seconds 8130.08 # Real time elapsed on the host sim_insts 896366789 # Number of instructions simulated sim_ops 1054186264 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 107072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 78336 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 7782464 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 12802520 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 15762560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 159744 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 154688 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3994240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 12481056 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 14503040 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 448448 # Number of bytes read from this memory system.physmem.bytes_read::total 68274168 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 7782464 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 3994240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 11776704 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 79542656 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 79563472 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1673 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1224 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 121601 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 200061 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 246290 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2496 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2417 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 62410 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 195031 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 226610 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 7007 # Number of read requests responded to by this memory system.physmem.num_reads::total 1066820 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1242854 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1245457 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 2259 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 1653 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 164195 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 270109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 332560 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 3370 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3264 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 84271 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 263327 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 305987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9461 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1440456 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 164195 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 84271 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 248466 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1678200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1678639 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1678200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 2259 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 1653 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 164195 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 270548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 332560 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 3370 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 84271 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 263327 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 305987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9461 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3119095 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1066820 # Number of read requests accepted system.physmem.writeReqs 1912174 # Number of write requests accepted system.physmem.readBursts 1066820 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1912174 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 68253568 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 22912 # Total number of bytes read from write queue system.physmem.bytesWritten 119234048 # Total number of bytes written to DRAM system.physmem.bytesReadSys 68274168 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 122233360 # Total written bytes from the system interface side system.physmem.servicedByWrQ 358 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 49121 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 113360 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 61922 # Per bank write bursts system.physmem.perBankRdBursts::1 70972 # Per bank write bursts system.physmem.perBankRdBursts::2 57667 # Per bank write bursts system.physmem.perBankRdBursts::3 64982 # Per bank write bursts system.physmem.perBankRdBursts::4 65050 # Per bank write bursts system.physmem.perBankRdBursts::5 70572 # Per bank write bursts system.physmem.perBankRdBursts::6 72322 # Per bank write bursts system.physmem.perBankRdBursts::7 67337 # Per bank write bursts system.physmem.perBankRdBursts::8 57787 # Per bank write bursts system.physmem.perBankRdBursts::9 110760 # Per bank write bursts system.physmem.perBankRdBursts::10 57283 # Per bank write bursts system.physmem.perBankRdBursts::11 63297 # Per bank write bursts system.physmem.perBankRdBursts::12 60054 # Per bank write bursts system.physmem.perBankRdBursts::13 63124 # Per bank write bursts system.physmem.perBankRdBursts::14 62259 # Per bank write bursts system.physmem.perBankRdBursts::15 61074 # Per bank write bursts system.physmem.perBankWrBursts::0 110998 # Per bank write bursts system.physmem.perBankWrBursts::1 120192 # Per bank write bursts system.physmem.perBankWrBursts::2 114368 # Per bank write bursts system.physmem.perBankWrBursts::3 118573 # Per bank write bursts system.physmem.perBankWrBursts::4 116138 # Per bank write bursts system.physmem.perBankWrBursts::5 119482 # Per bank write bursts system.physmem.perBankWrBursts::6 124701 # Per bank write bursts system.physmem.perBankWrBursts::7 122822 # Per bank write bursts system.physmem.perBankWrBursts::8 112747 # Per bank write bursts system.physmem.perBankWrBursts::9 113706 # Per bank write bursts system.physmem.perBankWrBursts::10 111725 # Per bank write bursts system.physmem.perBankWrBursts::11 114999 # Per bank write bursts system.physmem.perBankWrBursts::12 115986 # Per bank write bursts system.physmem.perBankWrBursts::13 114347 # Per bank write bursts system.physmem.perBankWrBursts::14 116931 # Per bank write bursts system.physmem.perBankWrBursts::15 115317 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 309 # Number of times write queue was full causing retry system.physmem.totGap 47397609004000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1066778 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1909571 # Write request sizes (log2) system.physmem.rdQLenPdf::0 706521 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 126151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 49462 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 37446 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 32271 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 29670 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 27253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 24519 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 21077 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 5735 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1704 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 954 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 743 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 468 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 414 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 346 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 284 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 44683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 64606 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 92963 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 104605 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 112793 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 111359 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 106848 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 102432 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 100351 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 96443 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 96232 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 115397 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 102859 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 98750 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 113669 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 102100 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 95328 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 90958 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 7555 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6743 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 6847 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 8326 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 7904 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 7101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5905 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 7422 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 5868 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 5697 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5505 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 5022 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 4736 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 3960 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 4047 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 3166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 2471 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1786 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 1553 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 1195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 1041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 906 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 935 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 725 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 739 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 598 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 535 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 533 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 628 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 443 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 770 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1060336 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 176.818458 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 107.808098 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 246.499626 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 676218 63.77% 63.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 204682 19.30% 83.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 51639 4.87% 87.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 24739 2.33% 90.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 18449 1.74% 92.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 11998 1.13% 93.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 8607 0.81% 93.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 7827 0.74% 94.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 56177 5.30% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1060336 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 82745 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 12.888404 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 137.186201 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 82742 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 82745 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 82745 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 22.515342 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 19.971264 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 20.554947 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-31 75024 90.67% 90.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-47 3669 4.43% 95.10% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-63 1611 1.95% 97.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-79 792 0.96% 98.01% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-95 419 0.51% 98.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-111 279 0.34% 98.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-127 435 0.53% 99.38% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-143 203 0.25% 99.62% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-159 68 0.08% 99.70% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-175 22 0.03% 99.73% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-191 73 0.09% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-207 36 0.04% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-223 10 0.01% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-239 7 0.01% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-255 4 0.00% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-271 3 0.00% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::272-287 1 0.00% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::288-303 7 0.01% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::320-335 7 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::336-351 11 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::352-367 22 0.03% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::384-399 2 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::400-415 4 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::592-607 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::656-671 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 82745 # Writes before turning the bus around for reads system.physmem.totQLat 40375015102 # Total ticks spent queuing system.physmem.totMemAccLat 60371177602 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5332310000 # Total ticks spent in databus transfers system.physmem.avgQLat 37858.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 56608.84 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.99 # Average write queue length when enqueuing system.physmem.readRowHits 803348 # Number of row buffer hits during reads system.physmem.writeRowHits 1065807 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate 57.21 # Row buffer hit rate for writes system.physmem.avgGap 15910609.09 # Average gap between requests system.physmem.pageHitRate 63.80 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4142388600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2260231875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 4140419400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 6138335520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1201204741230 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 27384875125500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 31698542432445 # Total energy per rank (pJ) system.physmem_0.averagePower 668.779401 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 45556660870724 # Time in different power states system.physmem_0.memoryStateTime::REF 1582710220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 258234748026 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3873751560 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2113654125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4177906200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 5934111840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 1188231262785 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 27396255369750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 31696367246580 # Total energy per rank (pJ) system.physmem_1.averagePower 668.733509 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 45575630122499 # Time in different power states system.physmem_1.memoryStateTime::REF 1582710220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 239268979001 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu0.branchPred.lookups 133516333 # Number of BP lookups system.cpu0.branchPred.condPredicted 94941201 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 6028887 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 100948341 # Number of BTB lookups system.cpu0.branchPred.BTBHits 73074204 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 72.387722 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 15498997 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 1074405 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.walker.walks 274493 # Table walker walks requested system.cpu0.dtb.walker.walksLong 274493 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8574 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74935 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walkWaitTime::samples 274493 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0 274493 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 274493 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkCompletionTime::samples 83509 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::0-65535 82824 99.18% 99.18% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::65536-131071 578 0.69% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-196607 32 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-262143 36 0.04% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::total 83509 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 74935 89.73% 89.73% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::2M 8574 10.27% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 83509 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 274493 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 274493 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 83509 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 83509 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin::total 358002 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 84777209 # DTB read hits system.cpu0.dtb.read_misses 227212 # DTB read misses system.cpu0.dtb.write_hits 75760151 # DTB write hits system.cpu0.dtb.write_misses 47281 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 33980 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 2153 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 9225 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 11068 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 85004421 # DTB read accesses system.cpu0.dtb.write_accesses 75807432 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 160537360 # DTB hits system.cpu0.dtb.misses 274493 # DTB misses system.cpu0.dtb.accesses 160811853 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.walker.walks 61212 # Table walker walks requested system.cpu0.itb.walker.walksLong 61212 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 587 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52411 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walkWaitTime::samples 61212 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0 61212 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 61212 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 52998 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::0-32767 48615 91.73% 91.73% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::32768-65535 3682 6.95% 98.68% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::65536-98303 228 0.43% 99.11% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-131071 379 0.72% 99.82% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.86% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.89% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::262144-294911 7 0.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 52998 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 52411 98.89% 98.89% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::2M 587 1.11% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 52998 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61212 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61212 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52998 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52998 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 114210 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 238748421 # ITB inst hits system.cpu0.itb.inst_misses 61212 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 24001 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 196095 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 238809633 # ITB inst accesses system.cpu0.itb.hits 238748421 # DTB hits system.cpu0.itb.misses 61212 # DTB misses system.cpu0.itb.accesses 238809633 # DTB accesses system.cpu0.numCycles 949769690 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 439719858 # Number of instructions committed system.cpu0.committedOps 516807751 # Number of ops (including micro ops) committed system.cpu0.discardedOps 45409758 # Number of ops (including micro ops) which were discarded before commit system.cpu0.numFetchSuspends 3855 # Number of times Execute suspended instruction fetching system.cpu0.quiesceCycles 93846100118 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.cpi 2.159943 # CPI: cycles per instruction system.cpu0.ipc 0.462975 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 12790 # number of quiesce instructions executed system.cpu0.tickCycles 712933683 # Number of cycles that the object actually ticked system.cpu0.idleCycles 236836007 # Total number of cycles that the object has spent stopped system.cpu0.dcache.tags.replacements 5519291 # number of replacements system.cpu0.dcache.tags.tagsinuse 480.702778 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 152151321 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 5519802 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 27.564634 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.702778 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938873 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.938873 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 207 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 323933952 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 323933952 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 77613049 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 77613049 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 70091195 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 70091195 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268191 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 268191 # number of SoftPFReq hits system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249696 # number of WriteInvalidateReq hits system.cpu0.dcache.WriteInvalidateReq_hits::total 249696 # number of WriteInvalidateReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1731388 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 1731388 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1698549 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1698549 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 147704244 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 147704244 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 147972435 # number of overall hits system.cpu0.dcache.overall_hits::total 147972435 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3327173 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3327173 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 2386267 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 2386267 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 673594 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 673594 # number of SoftPFReq misses system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 788040 # number of WriteInvalidateReq misses system.cpu0.dcache.WriteInvalidateReq_misses::total 788040 # number of WriteInvalidateReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148951 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 148951 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180566 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 180566 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 5713440 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 5713440 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 6387034 # number of overall misses system.cpu0.dcache.overall_misses::total 6387034 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 50124059800 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 50124059800 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46218650240 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 46218650240 # number of WriteReq miss cycles system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32570768827 # number of WriteInvalidateReq miss cycles system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32570768827 # number of WriteInvalidateReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2177391616 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 2177391616 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3839424984 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 3839424984 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3590500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3590500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 96342710040 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 96342710040 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 96342710040 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 96342710040 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 80940222 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 80940222 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 72477462 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 72477462 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 941785 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 941785 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1037736 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037736 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1880339 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 1880339 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1879115 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 1879115 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 153417684 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 153417684 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 154359469 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 154359469 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041107 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.041107 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032924 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.032924 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715231 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715231 # miss rate for SoftPFReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759384 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759384 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079215 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079215 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096091 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096091 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037241 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.037241 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041378 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.041378 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15065.059677 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 15065.059677 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19368.599675 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 19368.599675 # average WriteReq miss latency system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41331.364940 # average WriteInvalidateReq miss latency system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41331.364940 # average WriteInvalidateReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14618.173869 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14618.173869 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21263.277605 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21263.277605 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16862.469903 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 16862.469903 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15084.107904 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 15084.107904 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 3800112 # number of writebacks system.cpu0.dcache.writebacks::total 3800112 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429398 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 429398 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1005493 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1005493 # number of WriteReq MSHR hits system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 83 # number of WriteInvalidateReq MSHR hits system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 83 # number of WriteInvalidateReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41403 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41403 # number of LoadLockedReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 51 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 51 # number of StoreCondReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 1434891 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1434891 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 1434891 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1434891 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2897775 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 2897775 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380774 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1380774 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 667964 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 667964 # number of SoftPFReq MSHR misses system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 787957 # number of WriteInvalidateReq MSHR misses system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 787957 # number of WriteInvalidateReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 107548 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 107548 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180515 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 180515 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 4278549 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 4278549 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 4946513 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 4946513 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37570974686 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37570974686 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24854865946 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24854865946 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14971801156 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14971801156 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31379224673 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31379224673 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1379388880 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1379388880 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3557992992 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3557992992 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2840500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 62425840632 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 62425840632 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77397641788 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 77397641788 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5923264746 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5923264746 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5701581250 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5701581250 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11624845996 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11624845996 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035801 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035801 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019051 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019051 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.709253 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.709253 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759304 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759304 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057196 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057196 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096064 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096064 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027888 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.027888 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032045 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.032045 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12965.456147 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18000.676393 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18000.676393 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22414.083927 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927 # average SoftPFReq mshr miss latency system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219 # average WriteInvalidateReq mshr miss latency system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219 # average WriteInvalidateReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19710.234562 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19710.234562 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14590.423209 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14590.423209 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15646.909608 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15646.909608 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 9444901 # number of replacements system.cpu0.icache.tags.tagsinuse 511.930140 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 229100961 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 9445413 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 24.255261 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930140 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 486538188 # Number of tag accesses system.cpu0.icache.tags.data_accesses 486538188 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 229100961 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 229100961 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 229100961 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 229100961 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 229100961 # number of overall hits system.cpu0.icache.overall_hits::total 229100961 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 9445422 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 9445422 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 9445422 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 9445422 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 9445422 # number of overall misses system.cpu0.icache.overall_misses::total 9445422 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93680049293 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 93680049293 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 93680049293 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 93680049293 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 93680049293 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 93680049293 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 238546383 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 238546383 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 238546383 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 238546383 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 238546383 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 238546383 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039596 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.039596 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039596 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.039596 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039596 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.039596 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9918.037468 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 9918.037468 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9918.037468 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 9918.037468 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9918.037468 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 9918.037468 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9445422 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 9445422 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 9445422 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 9445422 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 9445422 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 9445422 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84206359153 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 84206359153 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84206359153 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 84206359153 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84206359153 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 84206359153 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039596 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.039596 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.039596 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8915.044680 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 7452732 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 7456615 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 3365 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 953257 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2717195 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16004.441587 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 15093815 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 2732791 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 5.523223 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 4841.451480 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.729529 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 10.200147 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6443.890934 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3592.570226 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1083.599270 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.295499 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001998 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000623 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.393304 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219273 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066138 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.976834 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1333 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 97 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14166 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 727 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 336 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 73 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5419 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5745 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081360 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005920 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.864624 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 323522928 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 323522928 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 471817 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 144979 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8688549 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.data 2694244 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 11999589 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 3800109 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 3800109 # number of Writeback hits system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 203236 # number of WriteInvalidateReq hits system.cpu0.l2cache.WriteInvalidateReq_hits::total 203236 # number of WriteInvalidateReq hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 106799 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 106799 # number of UpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33015 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 33015 # number of SCUpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 890572 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 890572 # number of ReadExReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 471817 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 144979 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 8688549 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.data 3584816 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 12890161 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 471817 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 144979 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 8688549 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.data 3584816 # number of overall hits system.cpu0.l2cache.overall_hits::total 12890161 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11486 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7971 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.inst 756872 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.data 978771 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 1755100 # number of ReadReq misses system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 582988 # number of WriteInvalidateReq misses system.cpu0.l2cache.WriteInvalidateReq_misses::total 582988 # number of WriteInvalidateReq misses system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124820 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 124820 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 147498 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 147498 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.data 270733 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 270733 # number of ReadExReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11486 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7971 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.inst 756872 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.data 1249504 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 2025833 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11486 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7971 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.inst 756872 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.data 1249504 # number of overall misses system.cpu0.l2cache.overall_misses::total 2025833 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 395323973 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 281388740 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22963858927 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32605245591 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 56245817231 # number of ReadReq miss cycles system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 226701268 # number of WriteInvalidateReq miss cycles system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 226701268 # number of WriteInvalidateReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2735720409 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 2735720409 # number of UpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3071526589 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3071526589 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2772000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2772000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13453990395 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 13453990395 # number of ReadExReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 395323973 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 281388740 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22963858927 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.data 46059235986 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 69699807626 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 395323973 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 281388740 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22963858927 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.data 46059235986 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 69699807626 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 483303 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 152950 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9445421 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3673015 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 13754689 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 3800110 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 3800110 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 786224 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.l2cache.WriteInvalidateReq_accesses::total 786224 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231619 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 231619 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180513 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 180513 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1161305 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1161305 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 483303 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 152950 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 9445421 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 4834320 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 14915994 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 483303 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 152950 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 9445421 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 4834320 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 14915994 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023766 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052115 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.080131 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266476 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.127600 # miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.741504 # miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.741504 # miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.538902 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.538902 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.817105 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.817105 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.233128 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.233128 # miss rate for ReadExReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023766 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052115 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080131 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258465 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.135816 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023766 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052115 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080131 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258465 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.135816 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34417.897702 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35301.560657 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30340.478875 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33312.435280 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32047.072663 # average ReadReq miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 388.860951 # average WriteInvalidateReq miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 388.860951 # average WriteInvalidateReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21917.324219 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21917.324219 # average UpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20824.191440 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20824.191440 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1386000 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1386000 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49694.682196 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49694.682196 # average ReadExReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34417.897702 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35301.560657 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30340.478875 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36862.015637 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 34405.505106 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34417.897702 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35301.560657 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30340.478875 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36862.015637 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 34405.505106 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.writebacks::writebacks 1419293 # number of writebacks system.cpu0.l2cache.writebacks::total 1419293 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 864 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 876 # number of ReadReq MSHR hits system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 21 # number of WriteInvalidateReq MSHR hits system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 21 # number of WriteInvalidateReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9600 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 9600 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10464 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 10476 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10464 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 10476 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11483 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7971 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 756863 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 977907 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 1754224 # number of ReadReq MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 730042 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 730042 # number of HardPFReq MSHR misses system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 582967 # number of WriteInvalidateReq MSHR misses system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 582967 # number of WriteInvalidateReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 124820 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 124820 # number of UpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 147498 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 147498 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261133 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 261133 # number of ReadExReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11483 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7971 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 756863 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1239040 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 2015357 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11483 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7971 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 756863 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1239040 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 730042 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 2745399 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 320171021 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 229236274 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 18018194823 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 26119410327 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 44687012445 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38329201084 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38329201084 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25353006103 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25353006103 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529620082 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529620082 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2203543880 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2203543880 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2330000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2330000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10429150296 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10429150296 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 320171021 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 229236274 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18018194823 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36548560623 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 55116162741 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 320171021 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 229236274 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18018194823 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36548560623 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38329201084 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 93445363825 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5656823753 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10047894503 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452375000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5452375000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11109198753 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15500269503 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.266241 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.127536 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741477 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741477 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.538902 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.538902 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817105 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817105 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224862 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224862 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135114 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.184057 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204 # average HardPFReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650 # average WriteInvalidateReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650 # average WriteInvalidateReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1165000 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1165000 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 16517621 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 14068332 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 33225 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 33225 # Transaction distribution system.cpu0.toL2Bus.trans_dist::Writeback 3800110 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 1086057 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1148168 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786224 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 477409 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332434 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 482483 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1303516 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1171227 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18995457 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16182353 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 335795 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1061304 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 36574909 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607854592 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 610383865 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1223600 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3866424 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 1223328481 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 4849156 # Total snoops (count) system.cpu0.toL2Bus.snoop_fanout::samples 24579773 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 3.184734 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.388082 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 20039056 81.53% 81.53% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 4540717 18.47% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 24579773 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 14682015163 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 205334987 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 14272912820 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 7968080178 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 183071466 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 578323929 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 139172899 # Number of BP lookups system.cpu1.branchPred.condPredicted 99233401 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 6252869 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 105205307 # Number of BTB lookups system.cpu1.branchPred.BTBHits 76618629 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 72.827722 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 16237430 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 1026400 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.walker.walks 295412 # Table walker walks requested system.cpu1.dtb.walker.walksLong 295412 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11437 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91734 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walkWaitTime::samples 295412 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0 295412 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 295412 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkCompletionTime::samples 103171 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::0-65535 101752 98.62% 98.62% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1198 1.16% 99.79% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::196608-262143 80 0.08% 99.90% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::total 103171 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 91734 88.91% 88.91% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::2M 11437 11.09% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 103171 # Table walker page sizes translated system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 295412 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 295412 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103171 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103171 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin::total 398583 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 90130445 # DTB read hits system.cpu1.dtb.read_misses 246227 # DTB read misses system.cpu1.dtb.write_hits 78064785 # DTB write hits system.cpu1.dtb.write_misses 49185 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 41873 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 864 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 7939 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 11435 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 90376672 # DTB read accesses system.cpu1.dtb.write_accesses 78113970 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 168195230 # DTB hits system.cpu1.dtb.misses 295412 # DTB misses system.cpu1.dtb.accesses 168490642 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.walker.walks 68039 # Table walker walks requested system.cpu1.itb.walker.walksLong 68039 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 556 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57997 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walkWaitTime::samples 68039 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 68039 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 68039 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 58553 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::0-65535 56928 97.22% 97.22% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-131071 1459 2.49% 99.72% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-196607 45 0.08% 99.79% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.15% 99.95% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 58553 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 57997 99.05% 99.05% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::2M 556 0.95% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 58553 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68039 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68039 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58553 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58553 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 126592 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 249268487 # ITB inst hits system.cpu1.itb.inst_misses 68039 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 30522 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 226060 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 249336526 # ITB inst accesses system.cpu1.itb.hits 249268487 # DTB hits system.cpu1.itb.misses 68039 # DTB misses system.cpu1.itb.accesses 249336526 # DTB accesses system.cpu1.numCycles 932637373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 456646931 # Number of instructions committed system.cpu1.committedOps 537378513 # Number of ops (including micro ops) committed system.cpu1.discardedOps 48077866 # Number of ops (including micro ops) which were discarded before commit system.cpu1.numFetchSuspends 5781 # Number of times Execute suspended instruction fetching system.cpu1.quiesceCycles 93863478723 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.cpi 2.042360 # CPI: cycles per instruction system.cpu1.ipc 0.489630 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 5811 # number of quiesce instructions executed system.cpu1.tickCycles 738281563 # Number of cycles that the object actually ticked system.cpu1.idleCycles 194355810 # Total number of cycles that the object has spent stopped system.cpu1.dcache.tags.replacements 5504177 # number of replacements system.cpu1.dcache.tags.tagsinuse 462.121005 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 159889231 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 5504689 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 29.046006 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.121005 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.902580 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.902580 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 339217340 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 339217340 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 82545716 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 82545716 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 72881068 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 72881068 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 234096 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 234096 # number of SoftPFReq hits system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 75438 # number of WriteInvalidateReq hits system.cpu1.dcache.WriteInvalidateReq_hits::total 75438 # number of WriteInvalidateReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1844359 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 1844359 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1835233 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1835233 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 155426784 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 155426784 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 155660880 # number of overall hits system.cpu1.dcache.overall_hits::total 155660880 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3601145 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3601145 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 2300638 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 2300638 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662253 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 662253 # number of SoftPFReq misses system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 453115 # number of WriteInvalidateReq misses system.cpu1.dcache.WriteInvalidateReq_misses::total 453115 # number of WriteInvalidateReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186074 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 186074 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193760 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 193760 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 5901783 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 5901783 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 6564036 # number of overall misses system.cpu1.dcache.overall_misses::total 6564036 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55051091271 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 55051091271 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39953352540 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 39953352540 # number of WriteReq miss cycles system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12827340347 # number of WriteInvalidateReq miss cycles system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12827340347 # number of WriteInvalidateReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2834422928 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 2834422928 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4003287927 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 4003287927 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3321500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3321500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 95004443811 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 95004443811 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 95004443811 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 95004443811 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 86146861 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 86146861 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 75181706 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 75181706 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 896349 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 896349 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 528553 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.dcache.WriteInvalidateReq_accesses::total 528553 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2030433 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 2030433 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2028993 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 2028993 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 161328567 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 161328567 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 162224916 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 162224916 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041802 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.041802 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030601 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.030601 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.738834 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.738834 # miss rate for SoftPFReq accesses system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.857274 # miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.857274 # miss rate for WriteInvalidateReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091643 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091643 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095496 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095496 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036582 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.036582 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040463 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.040463 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15287.107648 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 15287.107648 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17366.205609 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 17366.205609 # average WriteReq miss latency system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28309.237935 # average WriteInvalidateReq miss latency system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28309.237935 # average WriteInvalidateReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15232.772596 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15232.772596 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20661.064859 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16097.583359 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 16097.583359 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14473.480007 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 14473.480007 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 3506045 # number of writebacks system.cpu1.dcache.writebacks::total 3506045 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 409825 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 409825 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 940543 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 940543 # number of WriteReq MSHR hits system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 72 # number of WriteInvalidateReq MSHR hits system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 72 # number of WriteInvalidateReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45181 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45181 # number of LoadLockedReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.data 1350368 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 1350368 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.data 1350368 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 1350368 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3191320 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 3191320 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1360095 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 1360095 # number of WriteReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 661949 # number of SoftPFReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::total 661949 # number of SoftPFReq MSHR misses system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 453043 # number of WriteInvalidateReq MSHR misses system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 453043 # number of WriteInvalidateReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 140893 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 140893 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193713 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 193713 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 4551415 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 4551415 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 5213364 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 5213364 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42631813644 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42631813644 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22019784779 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22019784779 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605448576 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605448576 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12141090903 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12141090903 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1806083972 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1806083972 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3702335044 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3702335044 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2795500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2795500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64651598423 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 64651598423 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78257046999 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 78257046999 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 498907500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 498907500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 556628501 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 556628501 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1055536001 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1055536001 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037045 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037045 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.738495 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.738495 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.857138 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.857138 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069391 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069391 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095472 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095472 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028212 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.028212 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032137 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.032137 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309 # average WriteReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560 # average SoftPFReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560 # average SoftPFReq mshr miss latency system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340 # average WriteInvalidateReq mshr miss latency system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340 # average WriteInvalidateReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14204.724997 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14204.724997 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15010.854220 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15010.854220 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 9392574 # number of replacements system.cpu1.icache.tags.tagsinuse 507.206734 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 239643264 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 9393086 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 25.512730 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.206734 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990638 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.990638 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 507465788 # Number of tag accesses system.cpu1.icache.tags.data_accesses 507465788 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 239643264 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 239643264 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 239643264 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 239643264 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 239643264 # number of overall hits system.cpu1.icache.overall_hits::total 239643264 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 9393087 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 9393087 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 9393087 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 9393087 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 9393087 # number of overall misses system.cpu1.icache.overall_misses::total 9393087 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93629377858 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 93629377858 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 93629377858 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 93629377858 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 93629377858 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 93629377858 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 249036351 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 249036351 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 249036351 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 249036351 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 249036351 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 249036351 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037718 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.037718 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037718 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.037718 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037718 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.037718 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9967.902763 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 9967.902763 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 9967.902763 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 9967.902763 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9393087 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 9393087 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 9393087 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 9393087 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 9393087 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 9393087 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 84210400586 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 84210400586 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 84210400586 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 84210400586 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 84210400586 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 84210400586 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8117000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8117000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8117000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8117000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037718 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.037718 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.037718 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8965.146451 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 7598599 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 7600232 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 1400 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 976472 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2525133 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13593.944555 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 15352366 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 2541314 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 6.041113 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 9806300117000 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 4972.841269 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.331762 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.569688 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4463.050805 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3225.843213 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 763.307818 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.303518 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004964 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005345 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.272403 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.196890 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046589 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.829709 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1470 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 73 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14638 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 569 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 26 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1158 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5426 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.089722 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004456 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.893433 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 318573099 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 318573099 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 537712 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159577 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8583648 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.data 2948596 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 12229533 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 3506045 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 3506045 # number of Writeback hits system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 188584 # number of WriteInvalidateReq hits system.cpu1.l2cache.WriteInvalidateReq_hits::total 188584 # number of WriteInvalidateReq hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 74085 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 74085 # number of UpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41733 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 41733 # number of SCUpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 900308 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 900308 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 537712 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159577 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 8583648 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.data 3848904 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 13129841 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 537712 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159577 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 8583648 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.data 3848904 # number of overall hits system.cpu1.l2cache.overall_hits::total 13129841 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13252 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9078 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.inst 809439 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.data 1045283 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 1877052 # number of ReadReq misses system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 263334 # number of WriteInvalidateReq misses system.cpu1.l2cache.WriteInvalidateReq_misses::total 263334 # number of WriteInvalidateReq misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141894 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 141894 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151971 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 151971 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245370 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 245370 # number of ReadExReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13252 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9078 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.inst 809439 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.data 1290653 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 2122422 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13252 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9078 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.inst 809439 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.data 1290653 # number of overall misses system.cpu1.l2cache.overall_misses::total 2122422 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 492724981 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 392484013 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 23676424280 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34749867857 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 59311501131 # number of ReadReq miss cycles system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 207047946 # number of WriteInvalidateReq miss cycles system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 207047946 # number of WriteInvalidateReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3083845016 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 3083845016 # number of UpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3158531415 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3158531415 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2735500 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2735500 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10633257356 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 10633257356 # number of ReadExReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 492724981 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 392484013 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23676424280 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.data 45383125213 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 69944758487 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 492724981 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 392484013 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23676424280 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.data 45383125213 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 69944758487 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 550964 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168655 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9393087 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3993879 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 14106585 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 3506045 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 3506045 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 451918 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.l2cache.WriteInvalidateReq_accesses::total 451918 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 215979 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 215979 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193704 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 193704 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1145678 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1145678 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 550964 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168655 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 9393087 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 5139557 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 15252263 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 550964 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168655 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 9393087 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 5139557 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 15252263 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024052 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053826 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.086174 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.261721 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.133062 # miss rate for ReadReq accesses system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.582703 # miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.582703 # miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.656981 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.656981 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.784553 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784553 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.214170 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.214170 # miss rate for ReadExReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024052 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053826 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086174 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.251121 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.139155 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024052 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053826 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086174 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.251121 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.139155 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37181.178765 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43234.634611 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29250.412051 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 33244.459019 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31598.219512 # average ReadReq miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 786.256032 # average WriteInvalidateReq miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 786.256032 # average WriteInvalidateReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21733.441978 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21733.441978 # average UpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20783.777267 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20783.777267 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 303944.444444 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 303944.444444 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43335.604825 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43335.604825 # average ReadExReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37181.178765 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43234.634611 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29250.412051 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35162.917696 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 32955.160890 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37181.178765 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43234.634611 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29250.412051 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35162.917696 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 32955.160890 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 1067908 # number of writebacks system.cpu1.l2cache.writebacks::total 1067908 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 828 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 832 # number of ReadReq MSHR hits system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 3 # number of WriteInvalidateReq MSHR hits system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 3 # number of WriteInvalidateReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7579 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 7579 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8407 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 8411 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8407 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 8411 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13252 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9075 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 809438 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1044455 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 1876220 # number of ReadReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 726748 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 726748 # number of HardPFReq MSHR misses system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 263331 # number of WriteInvalidateReq MSHR misses system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 263331 # number of WriteInvalidateReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 141894 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 141894 # number of UpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 151971 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151971 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237791 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 237791 # number of ReadExReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13252 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9075 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 809438 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1282246 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 2114011 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13252 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9075 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 809438 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1282246 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 726748 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 2840759 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405848009 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 332680003 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 18392391220 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 27845262298 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 46976181530 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33709821360 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 33709821360 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8640486821 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8640486821 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2764991628 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2764991628 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2248670832 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2248670832 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2352000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2352000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8035534729 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8035534729 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405848009 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 332680003 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18392391220 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35880797027 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 55011716259 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405848009 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 332680003 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18392391220 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35880797027 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33709821360 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 88721537619 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7360000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 459163000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 466523000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 519410999 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 519410999 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7360000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 978573999 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 985933999 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.261514 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133003 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.582696 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.582696 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.656981 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.656981 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784553 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784553 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207555 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207555 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138603 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186252 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766 # average HardPFReq mshr miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011 # average WriteInvalidateReq mshr miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011 # average WriteInvalidateReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 16687989 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 14334572 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 4962 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 4962 # Transaction distribution system.cpu1.toL2Bus.trans_dist::Writeback 3506045 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 1053826 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1133141 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 451918 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 452249 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341136 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 469204 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1304040 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1151075 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18786353 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15676887 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371904 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1206650 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 36041794 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 601163264 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587975003 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349240 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4407712 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 1194895219 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 5002181 # Total snoops (count) system.cpu1.toL2Bus.snoop_fanout::samples 24473447 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 3.192626 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.394362 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 19759234 80.74% 80.74% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 4714213 19.26% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 24473447 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 13845201909 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 163397980 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 14102728136 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 8209870082 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 203661942 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 656138927 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40316 # Transaction distribution system.iobus.trans_dist::ReadResp 40316 # Transaction distribution system.iobus.trans_dist::WriteReq 136601 # Transaction distribution system.iobus.trans_dist::WriteResp 29873 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47648 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122530 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47668 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7496658 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36180000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer27.occupancy 607453407 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92660000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 148582123 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115592 # number of replacements system.iocache.tags.tagsinuse 11.295153 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9129697263000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 7.412327 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 3.882827 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.463270 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.242677 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.705947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040865 # Number of tag accesses system.iocache.tags.data_accesses 1040865 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses system.iocache.demand_misses::total 8924 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8884 # number of overall misses system.iocache.overall_misses::total 8924 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1659251745 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1664447245 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19947928539 # number of WriteInvalidateReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::total 19947928539 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::realview.ide 1659251745 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 1664816245 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles system.iocache.overall_miss_latency::realview.ide 1659251745 # number of overall miss cycles system.iocache.overall_miss_latency::total 1664816245 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::realview.ide 186768.544012 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 186576.308149 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186904.360046 # average WriteInvalidateReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::total 186904.360046 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency system.iocache.demand_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency system.iocache.demand_avg_miss_latency::total 186554.935567 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency system.iocache.overall_avg_miss_latency::total 186554.935567 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 112960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 16486 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 6.851874 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106678 # number of writebacks system.iocache.writebacks::total 106678 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196099891 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1199370391 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14397972639 # number of WriteInvalidateReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14397972639 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 1196099891 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 1199583391 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 1196099891 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 1199583391 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134635.287145 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 134443.491873 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134903.424022 # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134903.424022 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 1488066 # number of replacements system.l2c.tags.tagsinuse 64457.051863 # Cycle average of tags in use system.l2c.tags.total_refs 5017316 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1548603 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 3.239898 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 16300.231028 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.590542 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 5.410855 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 3923.984358 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 5628.040249 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3900.550479 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 368.152358 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 516.465158 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 4442.350927 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 11307.713496 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18045.562414 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.248722 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000284 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.059875 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.085877 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.059518 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005618 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.007881 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.067785 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.172542 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.275353 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.983537 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 10439 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 49850 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 337 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 10018 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 1727 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 4981 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 42979 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.159286 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.760651 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 65141561 # Number of tag accesses system.l2c.tags.data_accesses 65141561 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 6849 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 4798 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 687325 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 588389 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 296114 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 6913 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 4145 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 746877 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 598329 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 312912 # number of ReadReq hits system.l2c.ReadReq_hits::total 3252651 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 2487202 # number of Writeback hits system.l2c.Writeback_hits::total 2487202 # number of Writeback hits system.l2c.WriteInvalidateReq_hits::cpu0.data 134878 # number of WriteInvalidateReq hits system.l2c.WriteInvalidateReq_hits::cpu1.data 131392 # number of WriteInvalidateReq hits system.l2c.WriteInvalidateReq_hits::total 266270 # number of WriteInvalidateReq hits system.l2c.UpgradeReq_hits::cpu0.data 30237 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 30181 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 60418 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 6187 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 6142 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 12329 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 56549 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 53204 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109753 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 6849 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 4798 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 687325 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 644938 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 296114 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 6913 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 4145 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 746877 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 651533 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 312912 # number of demand (read+write) hits system.l2c.demand_hits::total 3362404 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 6849 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 4798 # number of overall hits system.l2c.overall_hits::cpu0.inst 687325 # number of overall hits system.l2c.overall_hits::cpu0.data 644938 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 296114 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 6913 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 4145 # number of overall hits system.l2c.overall_hits::cpu1.inst 746877 # number of overall hits system.l2c.overall_hits::cpu1.data 651533 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 312912 # number of overall hits system.l2c.overall_hits::total 3362404 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1673 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1224 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 69538 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 125760 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 246479 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2496 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 2417 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 62560 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 141194 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 226658 # number of ReadReq misses system.l2c.ReadReq_misses::total 879999 # number of ReadReq misses system.l2c.WriteInvalidateReq_misses::cpu0.data 439420 # number of WriteInvalidateReq misses system.l2c.WriteInvalidateReq_misses::cpu1.data 123627 # number of WriteInvalidateReq misses system.l2c.WriteInvalidateReq_misses::total 563047 # number of WriteInvalidateReq misses system.l2c.UpgradeReq_misses::cpu0.data 45454 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 42845 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 88299 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 9151 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 8719 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 17870 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 76776 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 56017 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 132793 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1673 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1224 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 69538 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 202536 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 246479 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2496 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 2417 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 62560 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 197211 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 226658 # number of demand (read+write) misses system.l2c.demand_misses::total 1012792 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1673 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1224 # number of overall misses system.l2c.overall_misses::cpu0.inst 69538 # number of overall misses system.l2c.overall_misses::cpu0.data 202536 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 246479 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2496 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 2417 # number of overall misses system.l2c.overall_misses::cpu1.inst 62560 # number of overall misses system.l2c.overall_misses::cpu1.data 197211 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 226658 # number of overall misses system.l2c.overall_misses::total 1012792 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 154004272 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 114242270 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 5875477080 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 11741177980 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 33542362820 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 221714757 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 213708998 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 5282320946 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 12643416993 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 28768061033 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 98556487149 # number of ReadReq miss cycles system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 54522296 # number of WriteInvalidateReq miss cycles system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41107699 # number of WriteInvalidateReq miss cycles system.l2c.WriteInvalidateReq_miss_latency::total 95629995 # number of WriteInvalidateReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 273262934 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 266190062 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 539452996 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 48096984 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56198212 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 104295196 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 6908017996 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 4749633793 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 11657651789 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 154004272 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 114242270 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 5875477080 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 18649195976 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33542362820 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 221714757 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 213708998 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 5282320946 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 17393050786 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 28768061033 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 110214138938 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 154004272 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 114242270 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 5875477080 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 18649195976 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33542362820 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 221714757 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 213708998 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 5282320946 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 17393050786 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 28768061033 # number of overall miss cycles system.l2c.overall_miss_latency::total 110214138938 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 8522 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 6022 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 756863 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 714149 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 542593 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 9409 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 6562 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 809437 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 739523 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 539570 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 4132650 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 2487202 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 2487202 # number of Writeback accesses(hits+misses) system.l2c.WriteInvalidateReq_accesses::cpu0.data 574298 # number of WriteInvalidateReq accesses(hits+misses) system.l2c.WriteInvalidateReq_accesses::cpu1.data 255019 # number of WriteInvalidateReq accesses(hits+misses) system.l2c.WriteInvalidateReq_accesses::total 829317 # number of WriteInvalidateReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 75691 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 73026 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 148717 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 15338 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 14861 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 30199 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 133325 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 109221 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 242546 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 8522 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 6022 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 756863 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 847474 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 542593 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 9409 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 6562 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 809437 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 848744 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 539570 # number of demand (read+write) accesses system.l2c.demand_accesses::total 4375196 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 8522 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 6022 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 756863 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 847474 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 542593 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 9409 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 6562 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 809437 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 848744 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 539570 # number of overall (read+write) accesses system.l2c.overall_accesses::total 4375196 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.196315 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.203255 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.091877 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.176098 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.454261 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.265278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.368333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.077288 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.190926 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.420072 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.212938 # miss rate for ReadReq accesses system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.765143 # miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.484776 # miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_miss_rate::total 0.678929 # miss rate for WriteInvalidateReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.600521 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.586709 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.593738 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.596623 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.586703 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.591741 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.575856 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.512878 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.547496 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.196315 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.203255 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.091877 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.238988 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.454261 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.265278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.368333 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.077288 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.232356 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.420072 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.231485 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.196315 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.203255 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.091877 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.238988 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.454261 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.265278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.368333 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.077288 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.232356 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.420072 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.231485 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92052.762702 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93335.187908 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84493.040927 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 93361.784192 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88828.027644 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88419.113777 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84436.076503 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 89546.418353 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 111996.135392 # average ReadReq miss latency system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 124.077866 # average WriteInvalidateReq miss latency system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 332.513925 # average WriteInvalidateReq miss latency system.l2c.WriteInvalidateReq_avg_miss_latency::total 169.843716 # average WriteInvalidateReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6011.856690 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6212.861757 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 6109.389642 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5255.926565 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6445.488244 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 5836.328819 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89976.268574 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84789.149597 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 87788.149895 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92052.762702 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93335.187908 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 84493.040927 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 92078.425445 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88828.027644 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88419.113777 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 84436.076503 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 88195.135089 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251 # average overall miss latency system.l2c.demand_avg_miss_latency::total 108822.086804 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92052.762702 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93335.187908 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 84493.040927 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 92078.425445 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88828.027644 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88419.113777 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 84436.076503 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 88195.135089 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251 # average overall miss latency system.l2c.overall_avg_miss_latency::total 108822.086804 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 2541 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 29 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs 87.620690 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 1136176 # number of writebacks system.l2c.writebacks::total 1136176 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 233 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 34 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 216 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 19 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 502 # number of ReadReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 233 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 35 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 216 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 503 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 233 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 35 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 216 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 503 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1673 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1224 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 69305 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 125726 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 246479 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2496 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2417 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 62344 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 141175 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 226658 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 879497 # number of ReadReq MSHR misses system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 439420 # number of WriteInvalidateReq MSHR misses system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 123627 # number of WriteInvalidateReq MSHR misses system.l2c.WriteInvalidateReq_mshr_misses::total 563047 # number of WriteInvalidateReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 45454 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 42845 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 88299 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9151 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8719 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 17870 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 76775 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 56017 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 132792 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1673 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1224 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 69305 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 202501 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 246479 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 2496 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 2417 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 62344 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 197192 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 226658 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 1012289 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1673 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1224 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 69305 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 202501 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 246479 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 2496 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 2417 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 62344 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 197192 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 226658 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 1012289 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 132900230 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 98791728 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4989728170 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10164730770 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30516558464 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 190282243 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 183250000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 4483732804 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10872787757 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25980768965 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 87613531131 # number of ReadReq MSHR miss cycles system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 14757449705 # number of WriteInvalidateReq MSHR miss cycles system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3963940301 # number of WriteInvalidateReq MSHR miss cycles system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18721390006 # number of WriteInvalidateReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 810939663 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 762507595 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 1573447258 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 163438118 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 155376174 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 318814292 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5948577254 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4049329707 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 9997906961 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 132900230 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 98791728 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 4989728170 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 16113308024 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30516558464 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 190282243 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 183250000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 4483732804 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 14922117464 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 25980768965 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 97611438092 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 132900230 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 98791728 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 4989728170 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 16113308024 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30516558464 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 190282243 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 183250000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 4483732804 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 14922117464 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25980768965 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 97611438092 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5006572250 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5293500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361466500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 8561345000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4837026001 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 427260001 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 5264286002 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9843598251 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5293500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 788726501 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 13825631002 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.176050 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.190900 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.212817 # mshr miss rate for ReadReq accesses system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.765143 # mshr miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.484776 # mshr miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.678929 # mshr miss rate for WriteInvalidateReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.600521 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586709 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.593738 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.596623 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.586703 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591741 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.575848 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512878 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.547492 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.231370 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.231370 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443 # average ReadReq mshr miss latency system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144 # average WriteInvalidateReq mshr miss latency system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201 # average WriteInvalidateReq mshr miss latency system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211 # average WriteInvalidateReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17840.886677 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 979077 # Transaction distribution system.membus.trans_dist::ReadResp 979077 # Transaction distribution system.membus.trans_dist::WriteReq 38187 # Transaction distribution system.membus.trans_dist::WriteResp 38187 # Transaction distribution system.membus.trans_dist::Writeback 1242854 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 666717 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 666717 # Transaction distribution system.membus.trans_dist::UpgradeReq 428866 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 287024 # Transaction distribution system.membus.trans_dist::UpgradeResp 113399 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution system.membus.trans_dist::ReadExReq 145453 # Transaction distribution system.membus.trans_dist::ReadExResp 128623 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122530 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25066 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5227832 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 5375480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336065 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 336065 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 5711545 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155660 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176401096 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 176608212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14106432 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 14106432 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 190714644 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 622043 # Total snoops (count) system.membus.snoop_fanout::samples 3659684 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 3659684 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 3659684 # Request fanout histogram system.membus.reqLayer0.occupancy 109555497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 20982498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 11300972211 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 6484776493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 151978377 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.toL2Bus.trans_dist::ReadReq 5072106 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 5064869 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38187 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38187 # Transaction distribution system.toL2Bus.trans_dist::Writeback 2487202 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 936242 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateResp 829317 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 482057 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 299353 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 781410 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 127 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 300573 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 300573 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8029813 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6984147 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 15013960 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269549433 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 226408539 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 495957972 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 1618057 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 9487188 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.012211 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.109827 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 9371339 98.78% 98.78% # Request fanout histogram system.toL2Bus.snoop_fanout::2 115849 1.22% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 9487188 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 8381122122 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 2527500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 4575963989 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 4435446795 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ----------