---------- Begin Simulation Statistics ---------- sim_seconds 2.837405 # Number of seconds simulated sim_ticks 2837404742000 # Number of ticks simulated final_tick 2837404742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 116559 # Simulator instruction rate (inst/s) host_op_rate 141347 # Simulator op (including micro ops) rate (op/s) host_tick_rate 2740803117 # Simulator tick rate (ticks/s) host_mem_usage 620980 # Number of bytes of host memory used host_seconds 1035.25 # Real time elapsed on the host sim_insts 120667663 # Number of instructions simulated sim_ops 146328933 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1294720 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 1292968 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 8487552 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 177584 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 590804 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 372608 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 12219756 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 1294720 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 177584 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1472304 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8624448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory system.physmem.bytes_written::total 8642012 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 22477 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 20723 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 132618 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2843 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 9252 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 5822 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 193790 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 134757 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory system.physmem.num_writes::total 139148 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 90 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 456304 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 455687 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 2991308 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 62587 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 208220 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 131320 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4306667 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 456304 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 62587 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 518891 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3039555 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3045745 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3039555 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 90 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 456304 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 461863 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 2991308 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 62587 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 208234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 131320 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7352412 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 193791 # Number of read requests accepted system.physmem.writeReqs 139148 # Number of write requests accepted system.physmem.readBursts 193791 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 139148 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 12392320 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue system.physmem.bytesWritten 8655168 # Total number of bytes written to DRAM system.physmem.bytesReadSys 12219820 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 8642012 # Total written bytes from the system interface side system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 12077 # Per bank write bursts system.physmem.perBankRdBursts::1 11849 # Per bank write bursts system.physmem.perBankRdBursts::2 12654 # Per bank write bursts system.physmem.perBankRdBursts::3 12755 # Per bank write bursts system.physmem.perBankRdBursts::4 14933 # Per bank write bursts system.physmem.perBankRdBursts::5 12164 # Per bank write bursts system.physmem.perBankRdBursts::6 12136 # Per bank write bursts system.physmem.perBankRdBursts::7 11937 # Per bank write bursts system.physmem.perBankRdBursts::8 12161 # Per bank write bursts system.physmem.perBankRdBursts::9 11860 # Per bank write bursts system.physmem.perBankRdBursts::10 11714 # Per bank write bursts system.physmem.perBankRdBursts::11 10962 # Per bank write bursts system.physmem.perBankRdBursts::12 11429 # Per bank write bursts system.physmem.perBankRdBursts::13 12078 # Per bank write bursts system.physmem.perBankRdBursts::14 11741 # Per bank write bursts system.physmem.perBankRdBursts::15 11180 # Per bank write bursts system.physmem.perBankWrBursts::0 8714 # Per bank write bursts system.physmem.perBankWrBursts::1 8695 # Per bank write bursts system.physmem.perBankWrBursts::2 9246 # Per bank write bursts system.physmem.perBankWrBursts::3 9229 # Per bank write bursts system.physmem.perBankWrBursts::4 8656 # Per bank write bursts system.physmem.perBankWrBursts::5 8632 # Per bank write bursts system.physmem.perBankWrBursts::6 8647 # Per bank write bursts system.physmem.perBankWrBursts::7 8231 # Per bank write bursts system.physmem.perBankWrBursts::8 8368 # Per bank write bursts system.physmem.perBankWrBursts::9 8311 # Per bank write bursts system.physmem.perBankWrBursts::10 8380 # Per bank write bursts system.physmem.perBankWrBursts::11 8024 # Per bank write bursts system.physmem.perBankWrBursts::12 8294 # Per bank write bursts system.physmem.perBankWrBursts::13 8191 # Per bank write bursts system.physmem.perBankWrBursts::14 8117 # Per bank write bursts system.physmem.perBankWrBursts::15 7502 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 16 # Number of times write queue was full causing retry system.physmem.totGap 2837404463500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 190125 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 134757 # Write request sizes (log2) system.physmem.rdQLenPdf::0 61827 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 74131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12988 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 9962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8314 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 7219 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 6282 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 5192 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 4551 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 813 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 555 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 227 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2623 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3607 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4664 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5751 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5631 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6168 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7663 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 7666 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 8574 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9601 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 8837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 9413 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 11928 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 9305 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 8281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 8065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 1451 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 493 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 415 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 324 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 280 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 257 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 60 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 87851 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 239.580927 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 135.192901 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 302.402140 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 47357 53.91% 53.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 17068 19.43% 73.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5804 6.61% 79.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3391 3.86% 83.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2670 3.04% 86.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1518 1.73% 88.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 937 1.07% 89.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 934 1.06% 90.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8172 9.30% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 87851 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6505 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 29.766180 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 576.399644 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 6503 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6505 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6505 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 20.789700 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 18.910113 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 14.034203 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 5345 82.17% 82.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 508 7.81% 89.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 102 1.57% 91.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 40 0.61% 92.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 39 0.60% 92.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 25 0.38% 93.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 50 0.77% 93.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 17 0.26% 94.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 116 1.78% 95.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 12 0.18% 96.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 7 0.11% 96.25% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 11 0.17% 96.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 77 1.18% 97.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 7 0.11% 97.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 5 0.08% 97.79% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 26 0.40% 98.19% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 87 1.34% 99.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 1 0.02% 99.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 2 0.03% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 5 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6505 # Writes before turning the bus around for reads system.physmem.totQLat 6373061511 # Total ticks spent queuing system.physmem.totMemAccLat 10003624011 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 968150000 # Total ticks spent in databus transfers system.physmem.avgQLat 32913.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 51663.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing system.physmem.readRowHits 161607 # Number of row buffer hits during reads system.physmem.writeRowHits 79408 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate 58.71 # Row buffer hit rate for writes system.physmem.avgGap 8522295.27 # Average gap between requests system.physmem.pageHitRate 73.28 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 346988880 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 189329250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 783931200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 453924000 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 185325366720 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 80760068955 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1631599751250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 1899459360255 # Total energy per rank (pJ) system.physmem_0.averagePower 669.435829 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 2714212324269 # Time in different power states system.physmem_0.memoryStateTime::REF 94747120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 28445283231 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 317164680 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 173056125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 726375000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 422411760 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 185325366720 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 80003948850 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 1632263014500 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 1899231337635 # Total energy per rank (pJ) system.physmem_1.averagePower 669.355466 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 2715316377598 # Time in different power states system.physmem_1.memoryStateTime::REF 94747120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 27339711152 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 39 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 39 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 39 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu0.branchPred.lookups 53928985 # Number of BP lookups system.cpu0.branchPred.condPredicted 24980647 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 980964 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 32646997 # Number of BTB lookups system.cpu0.branchPred.BTBHits 14259525 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 43.677907 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 15577797 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 34581 # Number of incorrect RAS predictions. system.cpu0.branchPred.indirectLookups 10158007 # Number of indirect predictor lookups. system.cpu0.branchPred.indirectHits 9989505 # Number of indirect target hits. system.cpu0.branchPred.indirectMisses 168502 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 52676 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.walker.walks 71164 # Table walker walks requested system.cpu0.dtb.walker.walksShort 71164 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25792 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21511 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 23861 # Table walks squashed before starting system.cpu0.dtb.walker.walkWaitTime::samples 47303 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::mean 513.360675 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::stdev 3057.570781 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0-8191 45975 97.19% 97.19% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::8192-16383 952 2.01% 99.21% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::16384-24575 188 0.40% 99.60% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.32% 99.92% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 47303 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkCompletionTime::samples 18252 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::mean 10854.262547 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::gmean 9468.640105 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::stdev 6407.913673 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::0-32767 18169 99.55% 99.55% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::32768-65535 76 0.42% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.03% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::total 18252 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 80034835468 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::mean 0.679509 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.477500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 25803805568 32.24% 32.24% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::1 54166837400 67.68% 99.92% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::2 30476500 0.04% 99.96% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::3 15818500 0.02% 99.98% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::4 5905000 0.01% 99.99% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::5 3281500 0.00% 99.99% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::6 3666500 0.00% 99.99% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::7 1298500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::8 960000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::9 729000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::11 276500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::12 755500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::14 120500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::15 122000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 80034835468 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 5842 79.40% 79.40% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::1M 1516 20.60% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 7358 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71164 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71164 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7358 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7358 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin::total 78522 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 24435903 # DTB read hits system.cpu0.dtb.read_misses 60770 # DTB read misses system.cpu0.dtb.write_hits 18100495 # DTB write hits system.cpu0.dtb.write_misses 10394 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 278 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 2366 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 972 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 24496673 # DTB read accesses system.cpu0.dtb.write_accesses 18110889 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 42536398 # DTB hits system.cpu0.dtb.misses 71164 # DTB misses system.cpu0.dtb.accesses 42607562 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.walker.walks 11512 # Table walker walks requested system.cpu0.itb.walker.walksShort 11512 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3903 # Level at which table walker walks with short descriptors terminate system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6443 # Level at which table walker walks with short descriptors terminate system.cpu0.itb.walker.walksSquashedBefore 1166 # Table walks squashed before starting system.cpu0.itb.walker.walkWaitTime::samples 10346 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::mean 443.263097 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::stdev 2195.478359 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0-4095 9924 95.92% 95.92% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::4096-8191 200 1.93% 97.85% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::8192-12287 136 1.31% 99.17% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::12288-16383 57 0.55% 99.72% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.81% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.14% 99.94% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::24576-28671 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 10346 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 4037 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::mean 11847.659153 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::gmean 10978.083476 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::stdev 5361.043324 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::0-16383 3811 94.40% 94.40% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::16384-32767 205 5.08% 99.48% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.47% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 4037 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 19905249824 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::mean 0.798667 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::stdev 0.401122 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 4008511500 20.14% 20.14% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::1 15895875324 79.86% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::2 793000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 19905249824 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2512 87.50% 87.50% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 359 12.50% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2871 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11512 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11512 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2871 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2871 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 14383 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 74030113 # ITB inst hits system.cpu0.itb.inst_misses 11512 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2605 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 2155 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 74041625 # ITB inst accesses system.cpu0.itb.hits 74030113 # DTB hits system.cpu0.itb.misses 11512 # DTB misses system.cpu0.itb.accesses 74041625 # DTB accesses system.cpu0.numCycles 210680851 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.fetch.icacheStallCycles 21171726 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 200049751 # Number of instructions fetch has processed system.cpu0.fetch.Branches 53928985 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 39826827 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 180241612 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 5811272 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 155130 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 70350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 431363 # Number of stall cycles due to pending traps system.cpu0.fetch.PendingQuiesceStallCycles 450452 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 103873 # Number of stall cycles due to full MSHR system.cpu0.fetch.CacheLines 74029415 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 271959 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 5637 # Number of outstanding ITLB misses that were squashed system.cpu0.fetch.rateDist::samples 205530142 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::mean 1.189019 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 1.306227 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::0 98403220 47.88% 47.88% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 31059279 15.11% 62.99% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 14883047 7.24% 70.23% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 61184596 29.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 205530142 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.255975 # Number of branch fetches per cycle system.cpu0.fetch.rate 0.949539 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 26358424 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 111125063 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 60339651 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 5146338 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 2560666 # Number of cycles decode is squashing system.cpu0.decode.BranchResolved 3166290 # Number of times decode resolved a branch system.cpu0.decode.BranchMispred 349435 # Number of times decode detected a branch misprediction system.cpu0.decode.DecodedInsts 158330686 # Number of instructions handled by decode system.cpu0.decode.SquashedInsts 3996082 # Number of squashed instructions handled by decode system.cpu0.rename.SquashCycles 2560666 # Number of cycles rename is squashing system.cpu0.rename.IdleCycles 35191325 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 13316748 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 85113900 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 56510449 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 12837054 # Number of cycles rename is unblocking system.cpu0.rename.RenamedInsts 141455630 # Number of instructions processed by rename system.cpu0.rename.SquashedInsts 1082284 # Number of squashed instructions processed by rename system.cpu0.rename.ROBFullEvents 1522598 # Number of times rename has blocked due to ROB full system.cpu0.rename.IQFullEvents 176451 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 63363 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 8486313 # Number of times rename has blocked due to SQ full system.cpu0.rename.RenamedOperands 145805955 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 652241827 # Number of register rename lookups that rename has made system.cpu0.rename.int_rename_lookups 157050612 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 10963 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 133960988 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 11844956 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 2734835 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 2587650 # count of temporary serializing insts renamed system.cpu0.rename.skidInsts 23017642 # count of insts added to the skid buffer system.cpu0.memDep0.insertedLoads 25406580 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 19629611 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 1770048 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 2573383 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 138387691 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 1764615 # Number of non-speculative instructions added to the IQ system.cpu0.iq.iqInstsIssued 136383682 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 482804 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 11087380 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedOperandsExamined 22916211 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 126267 # Number of squashed non-spec instructions that were removed system.cpu0.iq.issued_per_cycle::samples 205530142 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::mean 0.663570 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::stdev 0.962312 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::0 126796339 61.69% 61.69% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 34494575 16.78% 78.48% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 31991292 15.57% 94.04% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 11085283 5.39% 99.43% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::4 1162591 0.57% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 62 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::total 205530142 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 11095363 43.83% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 72 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.83% # attempts to use FU when none available system.cpu0.iq.fu_full::MemRead 5922142 23.40% 67.23% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 8295120 32.77% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued system.cpu0.iq.FU_type_0::IntAlu 91932498 67.41% 67.41% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 113960 0.08% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.49% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 67.50% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued system.cpu0.iq.FU_type_0::MemRead 25157178 18.45% 85.94% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 19169621 14.06% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 136383682 # Type of FU issued system.cpu0.iq.rate 0.647347 # Inst issue rate system.cpu0.iq.fu_busy_cnt 25312697 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.185599 # FU busy rate (busy events/executed inst) system.cpu0.iq.int_inst_queue_reads 504054876 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 151247362 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 132748931 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 38130 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 13196 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 11435 # Number of floating instruction queue wakeup accesses system.cpu0.iq.int_alu_accesses 161669314 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 24750 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 382212 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 2031269 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 20948 # Number of memory ordering violations system.cpu0.iew.lsq.thread0.squashedStores 944545 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 125569 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 392740 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 2560666 # Number of cycles IEW is squashing system.cpu0.iew.iewBlockCycles 1904881 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 242910 # Number of cycles IEW is unblocking system.cpu0.iew.iewDispatchedInsts 140340084 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispLoadInsts 25406580 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 19629611 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 903245 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 30849 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 186908 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 20948 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 273967 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 422470 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 696437 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 135301485 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 24689718 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1011162 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 187778 # number of nop insts executed system.cpu0.iew.exec_refs 43692090 # number of memory reference insts executed system.cpu0.iew.exec_branches 26150301 # Number of branches executed system.cpu0.iew.exec_stores 19002372 # Number of stores executed system.cpu0.iew.exec_rate 0.642211 # Inst execution rate system.cpu0.iew.wb_sent 134704568 # cumulative count of insts sent to commit system.cpu0.iew.wb_count 132760366 # cumulative count of insts written-back system.cpu0.iew.wb_producers 67768009 # num instructions producing a value system.cpu0.iew.wb_consumers 109468646 # num instructions consuming a value system.cpu0.iew.wb_rate 0.630149 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.619063 # average fanout of values written-back system.cpu0.commit.commitSquashedInsts 10008673 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 1638348 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 635994 # The number of times a branch was mispredicted system.cpu0.commit.committed_per_cycle::samples 202285941 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::mean 0.638783 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::stdev 1.339502 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::0 140398916 69.41% 69.41% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 34201466 16.91% 86.31% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 12970060 6.41% 92.73% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 3407217 1.68% 94.41% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::4 4957947 2.45% 96.86% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::5 2836864 1.40% 98.26% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 1346808 0.67% 98.93% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 576737 0.29% 99.21% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 1589926 0.79% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 202285941 # Number of insts commited each cycle system.cpu0.commit.committedInsts 106719327 # Number of instructions committed system.cpu0.commit.committedOps 129216760 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 42060376 # Number of memory references committed system.cpu0.commit.loads 23375310 # Number of loads committed system.cpu0.commit.membars 665131 # Number of memory barriers committed system.cpu0.commit.branches 25508530 # Number of branches committed system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. system.cpu0.commit.int_insts 112737159 # Number of committed integer instructions. system.cpu0.commit.function_calls 4888773 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu0.commit.op_class_0::IntAlu 87036683 67.36% 67.36% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 111592 0.09% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::MemRead 23375310 18.09% 85.54% # Class of committed instruction system.cpu0.commit.op_class_0::MemWrite 18685066 14.46% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 129216760 # Class of committed instruction system.cpu0.commit.bw_lim_events 1589926 # number cycles where commit BW limit reached system.cpu0.rob.rob_reads 316533140 # The number of ROB reads system.cpu0.rob.rob_writes 281685162 # The number of ROB writes system.cpu0.timesIdled 132617 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 5150709 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 5464128831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 106567484 # Number of Instructions Simulated system.cpu0.committedOps 129064917 # Number of Ops (including micro ops) Simulated system.cpu0.cpi 1.976971 # CPI: Cycles Per Instruction system.cpu0.cpi_total 1.976971 # CPI: Total CPI of All Threads system.cpu0.ipc 0.505824 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.505824 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 146676309 # number of integer regfile reads system.cpu0.int_regfile_writes 83772418 # number of integer regfile writes system.cpu0.fp_regfile_reads 9577 # number of floating regfile reads system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes system.cpu0.cc_regfile_reads 477802916 # number of cc regfile reads system.cpu0.cc_regfile_writes 51327219 # number of cc regfile writes system.cpu0.misc_regfile_reads 282498014 # number of misc regfile reads system.cpu0.misc_regfile_writes 1261276 # number of misc regfile writes system.cpu0.dcache.tags.replacements 747573 # number of replacements system.cpu0.dcache.tags.tagsinuse 499.341020 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 38792744 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 748085 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 51.856064 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.341020 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975275 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.975275 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 83715991 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 83715991 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 22140887 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 22140887 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 15403032 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 15403032 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 315432 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 315432 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371543 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 371543 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369802 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 369802 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 37543919 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 37543919 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 37859351 # number of overall hits system.cpu0.dcache.overall_hits::total 37859351 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 684637 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 684637 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 1972030 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1972030 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153419 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 153419 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25627 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 25627 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20274 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 20274 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 2656667 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2656667 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 2810086 # number of overall misses system.cpu0.dcache.overall_misses::total 2810086 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9946449500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 9946449500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36588625370 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 36588625370 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 415520500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 415520500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 535292500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 535292500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 777000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 777000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 46535074870 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 46535074870 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 46535074870 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 46535074870 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 22825524 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 22825524 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 17375062 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 17375062 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 468851 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 468851 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397170 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 397170 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390076 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 390076 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 40200586 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 40200586 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 40669437 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 40669437 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029994 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.029994 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113498 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.113498 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327223 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327223 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064524 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064524 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051974 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051974 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066085 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.066085 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069096 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.069096 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14528.063047 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14528.063047 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18553.787402 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 18553.787402 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16214.168650 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16214.168650 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26402.905199 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26402.905199 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17516.337151 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 17516.337151 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16560.018046 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 16560.018046 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 1975 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 5610717 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 211787 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.021277 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 26.492263 # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 747573 # number of writebacks system.cpu0.dcache.writebacks::total 747573 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276373 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 276373 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1635448 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1635448 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18943 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18943 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 1911821 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1911821 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911821 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1911821 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 408264 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 408264 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336582 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 336582 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106895 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 106895 # number of SoftPFReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6684 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6684 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20274 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 20274 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 744846 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 744846 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 851741 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 851741 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31822 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28485 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60307 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5115635000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115635000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7714022398 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7714022398 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1800093000 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1800093000 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 106991500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 106991500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 515034500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 515034500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 761000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 761000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12829657398 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 12829657398 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14629750398 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 14629750398 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6627444500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6627444500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6627444500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6627444500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017886 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017886 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019372 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019372 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227994 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227994 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016829 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016829 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051974 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051974 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018528 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.018528 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020943 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.020943 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12530.213293 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12530.213293 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22918.701529 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22918.701529 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16839.824126 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16839.824126 # average SoftPFReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16007.106523 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16007.106523 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25403.694387 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25403.694387 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17224.577158 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17224.577158 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17176.289973 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17176.289973 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208266.120923 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208266.120923 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109895.111679 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109895.111679 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 1304852 # number of replacements system.cpu0.icache.tags.tagsinuse 511.377336 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 72663769 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 1305364 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 55.665522 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 8205905000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377336 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 149356824 # Number of tag accesses system.cpu0.icache.tags.data_accesses 149356824 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 72663769 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 72663769 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 72663769 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 72663769 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 72663769 # number of overall hits system.cpu0.icache.overall_hits::total 72663769 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 1361937 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 1361937 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 1361937 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 1361937 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 1361937 # number of overall misses system.cpu0.icache.overall_misses::total 1361937 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14920933108 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 14920933108 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 14920933108 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 14920933108 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 14920933108 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 14920933108 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 74025706 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 74025706 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 74025706 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 74025706 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 74025706 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 74025706 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018398 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.018398 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018398 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.018398 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018398 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.018398 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10955.670569 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 10955.670569 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10955.670569 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 10955.670569 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10955.670569 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 10955.670569 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1976630 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1824 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 119804 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.498865 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 121.600000 # average number of cycles each access was blocked system.cpu0.icache.writebacks::writebacks 1304852 # number of writebacks system.cpu0.icache.writebacks::total 1304852 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56524 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 56524 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu0.inst 56524 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 56524 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu0.inst 56524 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 56524 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1305413 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 1305413 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 1305413 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 1305413 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 1305413 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 1305413 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13391499134 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 13391499134 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13391499134 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 13391499134 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13391499134 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 13391499134 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420576498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420576498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420576498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 420576498 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017635 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.017635 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.017635 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10258.438620 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 10258.438620 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 10258.438620 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886 # average overall mshr uncacheable latency system.cpu0.l2cache.prefetcher.num_hwpf_issued 1921401 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 1924253 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 2599 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 246531 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 284359 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16097.390005 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 3405020 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 300497 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 11.331294 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 14688.513215 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.811138 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.794692 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1396.270960 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.896516 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000721 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000049 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085222 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.982507 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 968 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15161 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 221 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 486 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4595 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7793 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2164 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059082 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925354 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 69247300 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 69247300 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60139 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13942 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 74081 # number of ReadReq hits system.cpu0.l2cache.WritebackDirty_hits::writebacks 504859 # number of WritebackDirty hits system.cpu0.l2cache.WritebackDirty_hits::total 504859 # number of WritebackDirty hits system.cpu0.l2cache.WritebackClean_hits::writebacks 1515130 # number of WritebackClean hits system.cpu0.l2cache.WritebackClean_hits::total 1515130 # number of WritebackClean hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205472 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 205472 # number of ReadExReq hits system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1249363 # number of ReadCleanReq hits system.cpu0.l2cache.ReadCleanReq_hits::total 1249363 # number of ReadCleanReq hits system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 423914 # number of ReadSharedReq hits system.cpu0.l2cache.ReadSharedReq_hits::total 423914 # number of ReadSharedReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60139 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13942 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 1249363 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.data 629386 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 1952830 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60139 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13942 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 1249363 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.data 629386 # number of overall hits system.cpu0.l2cache.overall_hits::total 1952830 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 355 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 452 # number of ReadReq misses system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55896 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 55896 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20274 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 20274 # number of SCUpgradeReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75415 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 75415 # number of ReadExReq misses system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 56005 # number of ReadCleanReq misses system.cpu0.l2cache.ReadCleanReq_misses::total 56005 # number of ReadCleanReq misses system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97807 # number of ReadSharedReq misses system.cpu0.l2cache.ReadSharedReq_misses::total 97807 # number of ReadSharedReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 355 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.inst 56005 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.data 173222 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 229679 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 355 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.inst 56005 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.data 173222 # number of overall misses system.cpu0.l2cache.overall_misses::total 229679 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11834000 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2688500 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 14522500 # number of ReadReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 189752500 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 189752500 # number of UpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43383500 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43383500 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 735000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 735000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4048179499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 4048179499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3814171500 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3814171500 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3421324998 # number of ReadSharedReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3421324998 # number of ReadSharedReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11834000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2688500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3814171500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.data 7469504497 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 11298198497 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11834000 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2688500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3814171500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.data 7469504497 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 11298198497 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60494 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14039 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 74533 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.WritebackDirty_accesses::writebacks 504859 # number of WritebackDirty accesses(hits+misses) system.cpu0.l2cache.WritebackDirty_accesses::total 504859 # number of WritebackDirty accesses(hits+misses) system.cpu0.l2cache.WritebackClean_accesses::writebacks 1515130 # number of WritebackClean accesses(hits+misses) system.cpu0.l2cache.WritebackClean_accesses::total 1515130 # number of WritebackClean accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55896 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 55896 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20274 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 20274 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280887 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 280887 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1305368 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 1305368 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 521721 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 521721 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60494 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14039 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1305368 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 802608 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 2182509 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60494 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14039 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1305368 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 802608 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 2182509 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005868 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.006909 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.006064 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.268489 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.268489 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042904 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042904 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.187470 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.187470 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005868 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.006909 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042904 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.215824 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.105236 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005868 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.006909 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042904 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.215824 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.105236 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33335.211268 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27716.494845 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32129.424779 # average ReadReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3394.742021 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3394.742021 # average UpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2139.858933 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2139.858933 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53678.704488 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53678.704488 # average ReadExReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68104.124632 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68104.124632 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34980.369483 # average ReadSharedReq miss latency system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34980.369483 # average ReadSharedReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33335.211268 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27716.494845 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68104.124632 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43120.992120 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 49191.256044 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33335.211268 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27716.494845 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68104.124632 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43120.992120 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 49191.256044 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25.750000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.unused_prefetches 10783 # number of HardPF blocks evicted w/o reference system.cpu0.l2cache.writebacks::writebacks 233335 # number of writebacks system.cpu0.l2cache.writebacks::total 233335 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32809 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 32809 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 49 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 49 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 794 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 794 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33603 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 33653 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33603 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 33653 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 355 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 96 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 451 # number of ReadReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259368 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 259368 # number of HardPFReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55896 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55896 # number of UpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20274 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20274 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42606 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 42606 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55956 # number of ReadCleanReq MSHR misses system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55956 # number of ReadCleanReq MSHR misses system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97013 # number of ReadSharedReq MSHR misses system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97013 # number of ReadSharedReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 355 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 96 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55956 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139619 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 196026 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 355 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 96 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55956 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139619 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259368 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 455394 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34825 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28485 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63310 # number of overall MSHR uncacheable misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9704000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2096500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11800500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21751180640 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21751180640 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1466856000 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1466856000 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 361881500 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 361881500 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 639000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 639000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2468105500 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2468105500 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3476206000 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3476206000 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2780887498 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2780887498 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9704000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2096500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3476206000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5248992998 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 8736999498 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9704000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2096500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3476206000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5248992998 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21751180640 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 30488180138 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398052500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6372573500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6770626000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398052500 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6372573500 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6770626000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006051 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151684 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151684 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042866 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.185948 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.185948 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173957 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089817 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173957 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208656 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26165.188470 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83862.236822 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26242.593388 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26242.593388 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.536352 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17849.536352 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57928.589870 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57928.589870 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62123.918793 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28665.101564 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28665.101564 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.119561 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44570.615622 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.119561 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66949.015881 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200256.850606 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194418.549892 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105668.885867 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106944.021482 # average overall mshr uncacheable latency system.cpu0.toL2Bus.snoop_filter.tot_requests 4258986 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2151003 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32472 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.snoop_filter.tot_snoops 329266 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 120454 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1996565 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28485 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28485 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WritebackDirty 738714 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WritebackClean 1547561 # Transaction distribution system.cpu0.toL2Bus.trans_dist::CleanEvict 211301 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 317009 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 86208 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42633 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 113720 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 299261 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 296052 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1305413 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592862 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 3357 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3921638 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727487 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129308 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 6809261 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167102064 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103511640 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56156 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 241976 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 270911836 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 1020612 # Total snoops (count) system.cpu0.toL2Bus.snoop_fanout::samples 3240855 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 0.120146 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.330026 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 2856673 88.15% 88.15% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 378987 11.69% 99.84% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 5195 0.16% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 3240855 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 4259428994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 115114135 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 1961743252 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 1289450748 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 16799978 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 68856412 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 3975194 # Number of BP lookups system.cpu1.branchPred.condPredicted 2297364 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 224488 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 2012976 # Number of BTB lookups system.cpu1.branchPred.BTBHits 1308063 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 64.981550 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 784876 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 5668 # Number of incorrect RAS predictions. system.cpu1.branchPred.indirectLookups 213732 # Number of indirect predictor lookups. system.cpu1.branchPred.indirectHits 189273 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 24459 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 5870 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.walker.walks 15858 # Table walker walks requested system.cpu1.dtb.walker.walksShort 15858 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8476 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3068 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 4314 # Table walks squashed before starting system.cpu1.dtb.walker.walkWaitTime::samples 11544 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::mean 612.006237 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::stdev 3319.733995 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0-4095 11004 95.32% 95.32% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::4096-8191 170 1.47% 96.79% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::8192-12287 217 1.88% 98.67% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.30% 98.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::16384-20479 27 0.23% 99.21% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.14% 99.35% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.38% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.53% 99.91% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 11544 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkCompletionTime::samples 3223 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::mean 11620.074465 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::gmean 10250.129632 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::stdev 7588.563203 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::0-16383 2748 85.26% 85.26% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::16384-32767 431 13.37% 98.63% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.09% 99.72% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::49152-65535 6 0.19% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-147455 2 0.06% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::total 3223 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 88338958560 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::mean 0.197151 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::stdev 0.399884 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 70951902092 80.32% 80.32% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::1 17371924968 19.67% 99.98% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::2 10393500 0.01% 99.99% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::3 1802000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::4 890500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::5 405500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::6 991000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::7 249000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::8 24000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::9 135000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::10 9000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::11 41000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::12 36000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::13 10500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::14 6000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::15 138500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 88338958560 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 1231 73.23% 73.23% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::1M 450 26.77% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 1681 # Table walker page sizes translated system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15858 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15858 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1681 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1681 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin::total 17539 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 3568678 # DTB read hits system.cpu1.dtb.read_misses 13961 # DTB read misses system.cpu1.dtb.write_hits 3021632 # DTB write hits system.cpu1.dtb.write_misses 1897 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1646 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 39 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 351 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 3582639 # DTB read accesses system.cpu1.dtb.write_accesses 3023529 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 6590310 # DTB hits system.cpu1.dtb.misses 15858 # DTB misses system.cpu1.dtb.accesses 6606168 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.walker.walks 5405 # Table walker walks requested system.cpu1.itb.walker.walksShort 5405 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2736 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2193 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksSquashedBefore 476 # Table walks squashed before starting system.cpu1.itb.walker.walkWaitTime::samples 4929 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::mean 233.921688 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::stdev 1867.315872 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0-4095 4828 97.95% 97.95% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::4096-8191 62 1.26% 99.21% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::8192-12287 17 0.34% 99.55% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.14% 99.70% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.04% 99.74% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::24576-28671 8 0.16% 99.90% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.04% 99.94% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 4929 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1313 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 11012.566641 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::gmean 10237.942197 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::stdev 4989.359306 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::0-8191 243 18.51% 18.51% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::8192-16383 995 75.78% 94.29% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::16384-24575 50 3.81% 98.10% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::24576-32767 10 0.76% 98.86% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.61% 99.47% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.30% 99.77% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.92% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.08% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1313 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 15319490028 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::mean 0.914748 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::stdev 0.279455 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1306821764 8.53% 8.53% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::1 14011918764 91.46% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::2 701000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::3 48500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 15319490028 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 694 82.92% 82.92% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 143 17.08% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5405 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5405 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 6242 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 7144027 # ITB inst hits system.cpu1.itb.inst_misses 5405 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 383 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 7149432 # ITB inst accesses system.cpu1.itb.hits 7144027 # DTB hits system.cpu1.itb.misses 5405 # DTB misses system.cpu1.itb.accesses 7149432 # DTB accesses system.cpu1.numCycles 32549087 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.fetch.icacheStallCycles 8029847 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 21178907 # Number of instructions fetch has processed system.cpu1.fetch.Branches 3975194 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 2282212 # Number of branches that fetch has predicted taken system.cpu1.fetch.Cycles 22801485 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 668344 # Number of cycles fetch has spent squashing system.cpu1.fetch.TlbCycles 75754 # Number of cycles fetch has spent waiting for tlb system.cpu1.fetch.MiscStallCycles 30605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.PendingTrapStallCycles 165807 # Number of stall cycles due to pending traps system.cpu1.fetch.PendingQuiesceStallCycles 282475 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 16137 # Number of stall cycles due to full MSHR system.cpu1.fetch.CacheLines 7143243 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 97050 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.ItlbSquashes 1864 # Number of outstanding ITLB misses that were squashed system.cpu1.fetch.rateDist::samples 31736282 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 0.814476 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 1.191251 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::0 19759016 62.26% 62.26% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 4355316 13.72% 75.98% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 1372720 4.33% 80.31% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 6249230 19.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 31736282 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.branchRate 0.122129 # Number of branch fetches per cycle system.cpu1.fetch.rate 0.650676 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 6554868 # Number of cycles decode is idle system.cpu1.decode.BlockedCycles 16518365 # Number of cycles decode is blocked system.cpu1.decode.RunCycles 7517718 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 925247 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 220084 # Number of cycles decode is squashing system.cpu1.decode.BranchResolved 615416 # Number of times decode resolved a branch system.cpu1.decode.BranchMispred 116450 # Number of times decode detected a branch misprediction system.cpu1.decode.DecodedInsts 19951417 # Number of instructions handled by decode system.cpu1.decode.SquashedInsts 870614 # Number of squashed instructions handled by decode system.cpu1.rename.SquashCycles 220084 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 7767251 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 2357969 # Number of cycles rename is blocking system.cpu1.rename.serializeStallCycles 11576087 # count of cycles rename stalled for serializing inst system.cpu1.rename.RunCycles 7215568 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 2599323 # Number of cycles rename is unblocking system.cpu1.rename.RenamedInsts 18979477 # Number of instructions processed by rename system.cpu1.rename.SquashedInsts 138008 # Number of squashed instructions processed by rename system.cpu1.rename.ROBFullEvents 212778 # Number of times rename has blocked due to ROB full system.cpu1.rename.IQFullEvents 28608 # Number of times rename has blocked due to IQ full system.cpu1.rename.LQFullEvents 12545 # Number of times rename has blocked due to LQ full system.cpu1.rename.SQFullEvents 1724298 # Number of times rename has blocked due to SQ full system.cpu1.rename.RenamedOperands 18792497 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 88805063 # Number of register rename lookups that rename has made system.cpu1.rename.int_rename_lookups 21879536 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 17041996 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 1750501 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 370474 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 302824 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 2489623 # count of insts added to the skid buffer system.cpu1.memDep0.insertedLoads 3780648 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 3305194 # Number of stores inserted to the mem dependence unit. system.cpu1.memDep0.conflictingLoads 561156 # Number of conflicting loads. system.cpu1.memDep0.conflictingStores 470424 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 18301855 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 511708 # Number of non-speculative instructions added to the IQ system.cpu1.iq.iqInstsIssued 18248720 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 63617 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 1549546 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 3571368 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 37688 # Number of squashed non-spec instructions that were removed system.cpu1.iq.issued_per_cycle::samples 31736282 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::mean 0.575011 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 0.923740 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 20906070 65.87% 65.87% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 5429676 17.11% 82.98% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 3608533 11.37% 94.35% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::3 1566039 4.93% 99.29% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 225959 0.71% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 5 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::total 31736282 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 1149585 28.00% 28.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 664 0.02% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMult 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatDiv 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAdd 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAlu 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCmp 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCvt 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMisc 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMult 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShift 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 28.01% # attempts to use FU when none available system.cpu1.iq.fu_full::MemRead 1347729 32.82% 60.84% # attempts to use FU when none available system.cpu1.iq.fu_full::MemWrite 1608151 39.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued system.cpu1.iq.FU_type_0::IntAlu 11270903 61.76% 61.76% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 26506 0.15% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.91% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 3164 0.02% 61.93% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.93% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.93% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.93% # Type of FU issued system.cpu1.iq.FU_type_0::MemRead 3745042 20.52% 82.45% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 3203081 17.55% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 18248720 # Type of FU issued system.cpu1.iq.rate 0.560652 # Inst issue rate system.cpu1.iq.fu_busy_cnt 4106129 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.225009 # FU busy rate (busy events/executed inst) system.cpu1.iq.int_inst_queue_reads 72403468 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 20371628 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 17886914 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu1.iq.int_alu_accesses 22354825 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 72854 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 302030 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 600 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 8546 # Number of memory ordering violations system.cpu1.iew.lsq.thread0.squashedStores 208715 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 35721 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 53336 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewSquashCycles 220084 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 521586 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 152596 # Number of cycles IEW is unblocking system.cpu1.iew.iewDispatchedInsts 18819577 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu1.iew.iewDispLoadInsts 3780648 # Number of dispatched load instructions system.cpu1.iew.iewDispStoreInsts 3305194 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 269579 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 5003 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 142623 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 8546 # Number of memory order violations system.cpu1.iew.predictedTakenIncorrect 21067 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 96357 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 117424 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 18070032 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 3674514 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 162831 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 6014 # number of nop insts executed system.cpu1.iew.exec_refs 6835502 # number of memory reference insts executed system.cpu1.iew.exec_branches 2611240 # Number of branches executed system.cpu1.iew.exec_stores 3160988 # Number of stores executed system.cpu1.iew.exec_rate 0.555162 # Inst execution rate system.cpu1.iew.wb_sent 17973633 # cumulative count of insts sent to commit system.cpu1.iew.wb_count 17886914 # cumulative count of insts written-back system.cpu1.iew.wb_producers 8930641 # num instructions producing a value system.cpu1.iew.wb_consumers 13891389 # num instructions consuming a value system.cpu1.iew.wb_rate 0.549537 # insts written-back per cycle system.cpu1.iew.wb_fanout 0.642890 # average fanout of values written-back system.cpu1.commit.commitSquashedInsts 1385631 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 474020 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 110400 # The number of times a branch was mispredicted system.cpu1.commit.committed_per_cycle::samples 31408226 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::mean 0.549763 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::stdev 1.309086 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::0 23101421 73.55% 73.55% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::1 4945584 15.75% 89.30% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 1441278 4.59% 93.89% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::3 545057 1.74% 95.62% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::4 459061 1.46% 97.08% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::5 290803 0.93% 98.01% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 192288 0.61% 98.62% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 102090 0.33% 98.95% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 330644 1.05% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 31408226 # Number of insts commited each cycle system.cpu1.commit.committedInsts 14103243 # Number of instructions committed system.cpu1.commit.committedOps 17267080 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 6575097 # Number of memory references committed system.cpu1.commit.loads 3478618 # Number of loads committed system.cpu1.commit.membars 192402 # Number of memory barriers committed system.cpu1.commit.branches 2497510 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu1.commit.int_insts 15405118 # Number of committed integer instructions. system.cpu1.commit.function_calls 417187 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu1.commit.op_class_0::IntAlu 10663290 61.76% 61.76% # Class of committed instruction system.cpu1.commit.op_class_0::IntMult 25529 0.15% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.90% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMisc 3164 0.02% 61.92% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.92% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.92% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.92% # Class of committed instruction system.cpu1.commit.op_class_0::MemRead 3478618 20.15% 82.07% # Class of committed instruction system.cpu1.commit.op_class_0::MemWrite 3096479 17.93% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 17267080 # Class of committed instruction system.cpu1.commit.bw_lim_events 330644 # number cycles where commit BW limit reached system.cpu1.rob.rob_reads 48838333 # The number of ROB reads system.cpu1.rob.rob_writes 37625273 # The number of ROB writes system.cpu1.timesIdled 48215 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 812805 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 5641687887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 14100179 # Number of Instructions Simulated system.cpu1.committedOps 17264016 # Number of Ops (including micro ops) Simulated system.cpu1.cpi 2.308417 # CPI: Cycles Per Instruction system.cpu1.cpi_total 2.308417 # CPI: Total CPI of All Threads system.cpu1.ipc 0.433197 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.433197 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 20251179 # number of integer regfile reads system.cpu1.int_regfile_writes 11682425 # number of integer regfile writes system.cpu1.cc_regfile_reads 64899787 # number of cc regfile reads system.cpu1.cc_regfile_writes 5579511 # number of cc regfile writes system.cpu1.misc_regfile_reads 46382322 # number of misc regfile reads system.cpu1.misc_regfile_writes 351060 # number of misc regfile writes system.cpu1.dcache.tags.replacements 151453 # number of replacements system.cpu1.dcache.tags.tagsinuse 475.445915 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 5884950 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 151796 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 38.768808 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 94652365000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.445915 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.928605 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.928605 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 12967805 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 12967805 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 3097715 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 3097715 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 2551654 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 2551654 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42598 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 42598 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69930 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 69930 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61845 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 61845 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 5649369 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 5649369 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 5691967 # number of overall hits system.cpu1.dcache.overall_hits::total 5691967 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 178499 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 178499 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 318856 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 318856 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23937 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 23937 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17809 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 17809 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23272 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 23272 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 497355 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 497355 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 521292 # number of overall misses system.cpu1.dcache.overall_misses::total 521292 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3304865000 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 3304865000 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11283001947 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 11283001947 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363785500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 363785500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633675000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 633675000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1492000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1492000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 14587866947 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 14587866947 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 14587866947 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 14587866947 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 3276214 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 3276214 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2870510 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2870510 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66535 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 66535 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87739 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 87739 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85117 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 85117 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 6146724 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 6146724 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 6213259 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 6213259 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054483 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.054483 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111080 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.111080 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.359766 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.359766 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.202977 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.202977 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273412 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273412 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.080914 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.080914 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.083900 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.083900 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18514.753584 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 18514.753584 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35385.885625 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 35385.885625 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20427.059352 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20427.059352 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27229.073565 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27229.073565 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29330.894325 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 29330.894325 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27984.060655 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 27984.060655 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 1664555 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 30437 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.571429 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets 54.688537 # average number of cycles each access was blocked system.cpu1.dcache.writebacks::writebacks 151454 # number of writebacks system.cpu1.dcache.writebacks::total 151454 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 61419 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 61419 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 240138 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 240138 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12559 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12559 # number of LoadLockedReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.data 301557 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 301557 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.data 301557 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 301557 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117080 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 117080 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78718 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 78718 # number of WriteReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23077 # number of SoftPFReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::total 23077 # number of SoftPFReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5250 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5250 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23272 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 23272 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 195798 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 195798 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 218875 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 218875 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3052 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3052 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2407 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5459 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5459 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724704000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724704000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2823186957 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2823186957 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 411595000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 411595000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99724500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99724500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610417000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610417000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1478000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1478000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4547890957 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 4547890957 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4959485957 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4959485957 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433858500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433858500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 433858500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 433858500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035736 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035736 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027423 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027423 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346840 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346840 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059837 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059837 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273412 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273412 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031854 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.031854 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035227 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.035227 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14730.987359 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14730.987359 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35864.566643 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35864.566643 # average WriteReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17835.723881 # average SoftPFReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17835.723881 # average SoftPFReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18995.142857 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18995.142857 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26229.675146 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26229.675146 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23227.463799 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23227.463799 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22658.987810 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22658.987810 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142155.471822 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142155.471822 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79475.819747 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79475.819747 # average overall mshr uncacheable latency system.cpu1.icache.tags.replacements 550819 # number of replacements system.cpu1.icache.tags.tagsinuse 499.430777 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 6572284 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 551331 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 11.920759 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 79423447000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.430777 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975451 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975451 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 14837444 # Number of tag accesses system.cpu1.icache.tags.data_accesses 14837444 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 6572284 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 6572284 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 6572284 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 6572284 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 6572284 # number of overall hits system.cpu1.icache.overall_hits::total 6572284 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 570771 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 570771 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 570771 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 570771 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 570771 # number of overall misses system.cpu1.icache.overall_misses::total 570771 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5205454773 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 5205454773 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 5205454773 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 5205454773 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 5205454773 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 5205454773 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 7143055 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 7143055 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 7143055 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 7143055 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 7143055 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 7143055 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079906 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.079906 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079906 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.079906 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079906 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.079906 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9120.040740 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 9120.040740 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9120.040740 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 9120.040740 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9120.040740 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 9120.040740 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 475905 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 114 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 36443 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.058886 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets 114 # average number of cycles each access was blocked system.cpu1.icache.writebacks::writebacks 550819 # number of writebacks system.cpu1.icache.writebacks::total 550819 # number of writebacks system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19437 # number of ReadReq MSHR hits system.cpu1.icache.ReadReq_mshr_hits::total 19437 # number of ReadReq MSHR hits system.cpu1.icache.demand_mshr_hits::cpu1.inst 19437 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_hits::total 19437 # number of demand (read+write) MSHR hits system.cpu1.icache.overall_mshr_hits::cpu1.inst 19437 # number of overall MSHR hits system.cpu1.icache.overall_mshr_hits::total 19437 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 551334 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 551334 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 551334 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 551334 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 551334 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 551334 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4760291519 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 4760291519 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4760291519 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 4760291519 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4760291519 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 4760291519 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13829000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13829000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13829000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 13829000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077185 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.077185 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8634.133790 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 8634.133790 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 8634.133790 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135578.431373 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135578.431373 # average overall mshr uncacheable latency system.cpu1.l2cache.prefetcher.num_hwpf_issued 116080 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 116662 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 527 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 50226 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 32901 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15108.183095 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 1229209 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 48015 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 25.600521 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 14647.178223 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.951767 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.912776 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 448.140330 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.893993 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000607 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000178 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027352 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.922130 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 986 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14072 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 621 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 357 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 780 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2641 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10651 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060181 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858887 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 24271230 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 24271230 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12198 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5610 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 17808 # number of ReadReq hits system.cpu1.l2cache.WritebackDirty_hits::writebacks 93872 # number of WritebackDirty hits system.cpu1.l2cache.WritebackDirty_hits::total 93872 # number of WritebackDirty hits system.cpu1.l2cache.WritebackClean_hits::writebacks 597156 # number of WritebackClean hits system.cpu1.l2cache.WritebackClean_hits::total 597156 # number of WritebackClean hits system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17499 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 17499 # number of ReadExReq hits system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 540940 # number of ReadCleanReq hits system.cpu1.l2cache.ReadCleanReq_hits::total 540940 # number of ReadCleanReq hits system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 80908 # number of ReadSharedReq hits system.cpu1.l2cache.ReadSharedReq_hits::total 80908 # number of ReadSharedReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12198 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5610 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 540940 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.data 98407 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 657155 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12198 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5610 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 540940 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.data 98407 # number of overall hits system.cpu1.l2cache.overall_hits::total 657155 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 446 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 265 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 711 # number of ReadReq misses system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29202 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 29202 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23271 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 23271 # number of SCUpgradeReq misses system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32662 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 32662 # number of ReadExReq misses system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10393 # number of ReadCleanReq misses system.cpu1.l2cache.ReadCleanReq_misses::total 10393 # number of ReadCleanReq misses system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64493 # number of ReadSharedReq misses system.cpu1.l2cache.ReadSharedReq_misses::total 64493 # number of ReadSharedReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 446 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 265 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.inst 10393 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.data 97155 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 108259 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 446 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 265 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.inst 10393 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.data 97155 # number of overall misses system.cpu1.l2cache.overall_misses::total 108259 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10024000 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5436500 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 15460500 # number of ReadReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 66927000 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 66927000 # number of UpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 66665000 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 66665000 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1457000 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1457000 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1788683500 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 1788683500 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 627007000 # number of ReadCleanReq miss cycles system.cpu1.l2cache.ReadCleanReq_miss_latency::total 627007000 # number of ReadCleanReq miss cycles system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1473931999 # number of ReadSharedReq miss cycles system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1473931999 # number of ReadSharedReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10024000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5436500 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.inst 627007000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.data 3262615499 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 3905082999 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10024000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5436500 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.inst 627007000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.data 3262615499 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 3905082999 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12644 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 5875 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 18519 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.WritebackDirty_accesses::writebacks 93872 # number of WritebackDirty accesses(hits+misses) system.cpu1.l2cache.WritebackDirty_accesses::total 93872 # number of WritebackDirty accesses(hits+misses) system.cpu1.l2cache.WritebackClean_accesses::writebacks 597157 # number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.WritebackClean_accesses::total 597157 # number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29202 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 29202 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23272 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 23272 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50161 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 50161 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 551333 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 551333 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 145401 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 145401 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12644 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 5875 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 551333 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 195562 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12644 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 5875 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 551333 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 195562 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.035274 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045106 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.038393 # miss rate for ReadReq accesses system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000002 # miss rate for WritebackClean accesses system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000002 # miss rate for WritebackClean accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999957 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999957 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.651143 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.651143 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018851 # miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018851 # miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.443553 # miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.443553 # miss rate for ReadSharedReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.035274 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045106 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018851 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496799 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.141438 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.035274 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045106 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018851 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496799 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.141438 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22475.336323 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20515.094340 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21744.725738 # average ReadReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2291.863571 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2291.863571 # average UpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2864.724335 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2864.724335 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 54763.440696 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 54763.440696 # average ReadExReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60329.741172 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60329.741172 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22854.139193 # average ReadSharedReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22854.139193 # average ReadSharedReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22475.336323 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20515.094340 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60329.741172 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33581.550090 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 36071.670706 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22475.336323 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20515.094340 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60329.741172 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33581.550090 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 36071.670706 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 182 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 60.666667 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.unused_prefetches 513 # number of HardPF blocks evicted w/o reference system.cpu1.l2cache.writebacks::writebacks 26284 # number of writebacks system.cpu1.l2cache.writebacks::total 26284 # number of writebacks system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1003 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 1003 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 30 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1033 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 1035 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1033 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 1035 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 446 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 265 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19781 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 19781 # number of HardPFReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29202 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29202 # number of UpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23271 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23271 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31659 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 31659 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10391 # number of ReadCleanReq MSHR misses system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10391 # number of ReadCleanReq MSHR misses system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 64463 # number of ReadSharedReq MSHR misses system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 64463 # number of ReadSharedReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 446 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 265 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10391 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96122 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 107224 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 446 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 265 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10391 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96122 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19781 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 127005 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3052 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3154 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2407 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5459 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5561 # number of overall MSHR uncacheable misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3846500 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11194500 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1151290913 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1151290913 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 600355000 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 600355000 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 435611000 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 435611000 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1373000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1373000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1514716000 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1514716000 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 564636500 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 564636500 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1085937999 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1085937999 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3846500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 564636500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2600653999 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 3176484999 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3846500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 564636500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2600653999 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1151290913 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 4327775912 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13064000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 409389000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 422453000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13064000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 409389000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 422453000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038393 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackClean accesses system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackClean accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.631148 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.631148 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018847 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.443346 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.443346 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.491517 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140086 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.491517 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.165930 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15744.725738 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58201.855973 # average HardPFReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20558.694610 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20558.694610 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18719.049461 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18719.049461 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47844.720301 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47844.720301 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54338.995284 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16845.911593 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16845.911593 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27055.762458 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29624.757508 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27055.762458 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34075.634125 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134137.942333 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133941.978440 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 74993.405386 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75967.092250 # average overall mshr uncacheable latency system.cpu1.toL2Bus.snoop_filter.tot_requests 1509011 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 762131 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11245 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.snoop_filter.tot_snoops 172130 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2310 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 24888 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 759622 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2407 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2407 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WritebackDirty 121244 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WritebackClean 608400 # Transaction distribution system.cpu1.toL2Bus.trans_dist::CleanEvict 89967 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 23852 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 71187 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41516 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 57431 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 54716 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 551334 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224940 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1653690 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 733597 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12997 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27256 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 2427540 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70539360 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24952640 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 23500 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50576 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 95566076 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 366639 # Total snoops (count) system.cpu1.toL2Bus.snoop_fanout::samples 1114936 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 0.173156 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.383819 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 924188 82.89% 82.89% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 188438 16.90% 99.79% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 2310 0.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 1114936 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 1467946497 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 80180559 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 827154896 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 324971252 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 7123996 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 14622978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31018 # Transaction distribution system.iobus.trans_dist::ReadResp 31018 # Transaction distribution system.iobus.trans_dist::WriteReq 59424 # Transaction distribution system.iobus.trans_dist::WriteResp 59424 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40401000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 585000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 6085000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 34109000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 187090970 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements system.iocache.tags.tagsinuse 14.555535 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 256148567000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ide 14.555535 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.909721 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.909721 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 32635877 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 32635877 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4576397093 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4576397093 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 4609032970 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 4609032970 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 4609032970 # number of overall miss cycles system.iocache.overall_miss_latency::total 4609032970 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 129507.448413 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 129507.448413 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126336.050491 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126336.050491 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 126357.960577 # average overall miss latency system.iocache.demand_avg_miss_latency::total 126357.960577 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 126357.960577 # average overall miss latency system.iocache.overall_avg_miss_latency::total 126357.960577 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 20035877 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 20035877 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763475432 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2763475432 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 2783511309 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 2783511309 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 2783511309 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 2783511309 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79507.448413 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 79507.448413 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76288.522306 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76288.522306 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 76310.760747 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 76310.760747 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 76310.760747 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76310.760747 # average overall mshr miss latency system.l2c.tags.replacements 125494 # number of replacements system.l2c.tags.tagsinuse 63202.959531 # Cycle average of tags in use system.l2c.tags.total_refs 439435 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 189556 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.318233 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 13071.247488 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.199813 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 1.970724 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 8317.166173 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 2997.468102 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34883.534763 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.576740 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910038 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 1686.284360 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 475.918503 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1747.682827 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.199451 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000232 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.126910 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.045738 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.532280 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.025731 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.007262 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026668 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.964401 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 30884 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 33156 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 5810 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 24946 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 618 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 4320 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 28181 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.471252 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.505920 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 6014054 # Number of tag accesses system.l2c.tags.data_accesses 6014054 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 259619 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 259619 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 32746 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1957 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 34703 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 2097 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 869 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2966 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 1360 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 5338 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 199 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.inst 36469 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.data 49080 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47369 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 28 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 11 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.inst 7634 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 4971 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3115 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 148940 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 199 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 36469 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 53058 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 47369 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 7634 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 6331 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 3115 # number of demand (read+write) hits system.l2c.demand_hits::total 154278 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 199 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits system.l2c.overall_hits::cpu0.inst 36469 # number of overall hits system.l2c.overall_hits::cpu0.data 53058 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 47369 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 28 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 11 # number of overall hits system.l2c.overall_hits::cpu1.inst 7634 # number of overall hits system.l2c.overall_hits::cpu1.data 6331 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 3115 # number of overall hits system.l2c.overall_hits::total 154278 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 10077 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2519 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12596 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 841 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1321 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2162 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 11292 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 8274 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 19566 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.inst 19487 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.data 9131 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132775 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.inst 2756 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 977 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5822 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 170988 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 19487 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 20423 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 132775 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2756 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 9251 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 5822 # number of demand (read+write) misses system.l2c.demand_misses::total 190554 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.inst 19487 # number of overall misses system.l2c.overall_misses::cpu0.data 20423 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 132775 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 2756 # number of overall misses system.l2c.overall_misses::cpu1.data 9251 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 5822 # number of overall misses system.l2c.overall_misses::total 190554 # number of overall misses system.l2c.UpgradeReq_miss_latency::cpu0.data 30450500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 6079500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 36530000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4673500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3850000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 8523500 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 1715723499 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 1100336500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 2816059999 # number of ReadExReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3865000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 526500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2588066000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 1270606500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20899436571 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1078000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 146500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.inst 371480000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 137505000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1077632372 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 26350342443 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 3865000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 526500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 2588066000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 2986329999 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20899436571 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 1078000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 146500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 371480000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 1237841500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1077632372 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 29166402442 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 3865000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 526500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 2588066000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 2986329999 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20899436571 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 1078000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 146500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 371480000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 1237841500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1077632372 # number of overall miss cycles system.l2c.overall_miss_latency::total 29166402442 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 259619 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 259619 # number of WritebackDirty accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 42823 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 4476 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 47299 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 2938 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2190 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 5128 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 15270 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 9634 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 24904 # number of ReadExReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 226 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 68 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.inst 55956 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.data 58211 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180144 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.inst 10390 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 5948 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8937 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::total 319928 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 226 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 68 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 55956 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 73481 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180144 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 10390 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 15582 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8937 # number of demand (read+write) accesses system.l2c.demand_accesses::total 344832 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 226 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 68 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 55956 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 73481 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180144 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 10390 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 15582 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8937 # number of overall (read+write) accesses system.l2c.overall_accesses::total 344832 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.235317 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.562779 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.266306 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.286249 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.603196 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.421607 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.739489 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.858833 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.785657 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.119469 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.348256 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.156860 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.737049 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222222 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.083333 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.265255 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164257 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.651449 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.534458 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.119469 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.348256 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.277936 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737049 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222222 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.083333 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.265255 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.593698 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.651449 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.552600 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.119469 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.348256 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.277936 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737049 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222222 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.083333 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.265255 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.593698 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.651449 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.552600 # miss rate for overall accesses system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3021.782276 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2413.457721 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 2900.127024 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5557.074911 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2914.458743 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 3942.414431 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151941.507173 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132987.249214 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 143926.198457 # average ReadExReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143148.148148 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 131625 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132809.873249 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139153.050049 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 134750 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 146500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134789.550073 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140742.067554 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 154106.384325 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143148.148148 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 131625 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 132809.873249 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 146223.865201 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 134750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 146500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 134789.550073 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 133806.237164 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297 # average overall miss latency system.l2c.demand_avg_miss_latency::total 153061.087366 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143148.148148 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 131625 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 132809.873249 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 146223.865201 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 146500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 134789.550073 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 133806.237164 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297 # average overall miss latency system.l2c.overall_avg_miss_latency::total 153061.087366 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 270 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 98551 # number of writebacks system.l2c.writebacks::total 98551 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 2889 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 2889 # number of CleanEvict MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 10077 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 2519 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 12596 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 841 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1321 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2162 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 11292 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 8274 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 19566 # number of ReadExReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19484 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9131 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132775 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2752 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.data 977 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5822 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::total 170981 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 19484 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 20423 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132775 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 2752 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 9251 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5822 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 190547 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 19484 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 20423 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132775 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 2752 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 9251 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5822 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 190547 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3049 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 37976 # number of ReadReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 30892 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5456 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 68868 # number of overall MSHR uncacheable misses system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 733108000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 182446000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 915554000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 62803500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97589000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 160392500 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1602798509 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1017587525 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 2620386034 # number of ReadExReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3595000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 486500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2392931045 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1179292009 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19571641713 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 998000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 136500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 343537535 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 127733004 # 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number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 343537535 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1145320529 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1019394964 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 27260132304 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343998000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5799755006 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11227000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 354456000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 6509436006 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343998000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5799755006 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11227000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 354456000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 6509436006 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.235317 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.562779 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.266306 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.286249 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.603196 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.421607 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739489 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.858833 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.785657 # mshr miss rate for ReadExReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.119469 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.058824 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.348202 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.156860 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737049 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222222 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.264870 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164257 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.651449 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.534436 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.119469 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.058824 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.348202 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.277936 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737049 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222222 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.264870 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.593698 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.651449 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.552579 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.119469 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.058824 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.348202 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.277936 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737049 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222222 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.264870 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.593698 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.651449 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.552579 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72750.620224 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72427.947598 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72686.090822 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74677.170036 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73875.094625 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.095282 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141941.065267 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122986.164491 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 133925.484718 # average ReadExReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 121625 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122815.183997 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129152.558208 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 124750 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 136500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124831.953125 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130740.024565 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144108.095461 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 121625 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122815.183997 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136223.400969 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124750 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 136500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124831.953125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123805.051238 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 143062.511107 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 121625 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122815.183997 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136223.400969 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124750 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 136500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124831.953125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123805.051238 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 143062.511107 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182256.143737 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110068.627451 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116253.197770 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171409.205972 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96170.510985 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110068.627451 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 64966.275660 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 94520.474037 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 37976 # Transaction distribution system.membus.trans_dist::ReadResp 209208 # Transaction distribution system.membus.trans_dist::WriteReq 30892 # Transaction distribution system.membus.trans_dist::WriteResp 30892 # Transaction distribution system.membus.trans_dist::WritebackDirty 134757 # Transaction distribution system.membus.trans_dist::CleanEvict 15369 # Transaction distribution system.membus.trans_dist::UpgradeReq 74473 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 40549 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 39381 # Transaction distribution system.membus.trans_dist::ReadExResp 19462 # Transaction distribution system.membus.trans_dist::ReadSharedReq 171233 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13654 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645275 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 766897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 839846 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27308 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18543624 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 18734032 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 21052176 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 120651 # Total snoops (count) system.membus.snoop_fanout::samples 580873 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 580873 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 580873 # Request fanout histogram system.membus.reqLayer0.occupancy 81906000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 11549500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 984548482 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 1099659305 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1332381 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.toL2Bus.snoop_filter.tot_requests 989892 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 534223 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 146584 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 20158 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 19282 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 876 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 37979 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 475706 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30892 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30892 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 394392 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 117024 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 109072 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 43515 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 152587 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 50322 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 50322 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 437743 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1265601 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 259494 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 1525095 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35019900 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3939924 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 38959824 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 441873 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 907771 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.341587 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.476273 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 598564 65.94% 65.94% # Request fanout histogram system.toL2Bus.snoop_fanout::1 308331 33.97% 99.90% # Request fanout histogram system.toL2Bus.snoop_fanout::2 876 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 907771 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 872211768 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 658378956 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 205665017 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1873 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed ---------- End Simulation Statistics ----------