---------- Begin Simulation Statistics ---------- sim_seconds 1.145505 # Number of seconds simulated sim_ticks 1145504982000 # Number of ticks simulated final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 113120 # Simulator instruction rate (inst/s) host_op_rate 136231 # Simulator op (including micro ops) rate (op/s) host_tick_rate 2095202848 # Simulator tick rate (ticks/s) host_mem_usage 413760 # Number of bytes of host memory used host_seconds 546.73 # Real time elapsed on the host sim_insts 61845931 # Number of instructions simulated sim_ops 74481224 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 6457305 # Number of read requests accepted system.physmem.writeReqs 823729 # Number of write requests accepted system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 403300 # Per bank write bursts system.physmem.perBankRdBursts::1 403658 # Per bank write bursts system.physmem.perBankRdBursts::2 403038 # Per bank write bursts system.physmem.perBankRdBursts::3 403410 # Per bank write bursts system.physmem.perBankRdBursts::4 406147 # Per bank write bursts system.physmem.perBankRdBursts::5 403703 # Per bank write bursts system.physmem.perBankRdBursts::6 403511 # Per bank write bursts system.physmem.perBankRdBursts::7 403334 # Per bank write bursts system.physmem.perBankRdBursts::8 403656 # Per bank write bursts system.physmem.perBankRdBursts::9 404136 # Per bank write bursts system.physmem.perBankRdBursts::10 403079 # Per bank write bursts system.physmem.perBankRdBursts::11 402530 # Per bank write bursts system.physmem.perBankRdBursts::12 403635 # Per bank write bursts system.physmem.perBankRdBursts::13 403544 # Per bank write bursts system.physmem.perBankRdBursts::14 403293 # Per bank write bursts system.physmem.perBankRdBursts::15 402900 # Per bank write bursts system.physmem.perBankWrBursts::0 6991 # Per bank write bursts system.physmem.perBankWrBursts::1 7395 # Per bank write bursts system.physmem.perBankWrBursts::2 6850 # Per bank write bursts system.physmem.perBankWrBursts::3 7056 # Per bank write bursts system.physmem.perBankWrBursts::4 7584 # Per bank write bursts system.physmem.perBankWrBursts::5 7290 # Per bank write bursts system.physmem.perBankWrBursts::6 7311 # Per bank write bursts system.physmem.perBankWrBursts::7 7141 # Per bank write bursts system.physmem.perBankWrBursts::8 7309 # Per bank write bursts system.physmem.perBankWrBursts::9 7743 # Per bank write bursts system.physmem.perBankWrBursts::10 6877 # Per bank write bursts system.physmem.perBankWrBursts::11 6465 # Per bank write bursts system.physmem.perBankWrBursts::12 7382 # Per bank write bursts system.physmem.perBankWrBursts::13 7153 # Per bank write bursts system.physmem.perBankWrBursts::14 7067 # Per bank write bursts system.physmem.perBankWrBursts::15 6768 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 1145502120500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 6291481 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 165765 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66893 # Write request sizes (log2) system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3952 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6658 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 6662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 6658 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 6669 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 6657 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 6652 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads system.physmem.totQLat 165525335000 # Total ticks spent queuing system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.87 # Data bus utilization in percentage system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing system.physmem.readRowHits 6016106 # Number of row buffer hits during reads system.physmem.writeRowHits 94363 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes system.physmem.avgGap 157326.85 # Average gap between requests system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states system.physmem.memoryStateTime::REF 38250680000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 61688542 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 7506218 # Transaction distribution system.membus.trans_dist::ReadResp 7506218 # Transaction distribution system.membus.trans_dist::WriteReq 767823 # Transaction distribution system.membus.trans_dist::WriteResp 767823 # Transaction distribution system.membus.trans_dist::Writeback 66893 # Transaction distribution system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution system.membus.trans_dist::ReadExReq 137868 # Transaction distribution system.membus.trans_dist::ReadExResp 137512 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 70664532 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 8866177000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 4931588399 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 73238 # number of replacements system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 23040420 # Number of tag accesses system.l2c.tags.data_accesses 23040420 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits system.l2c.Writeback_hits::total 575172 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits system.l2c.overall_hits::total 2074936 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 16107 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 9802 # number of ReadReq misses system.l2c.ReadReq_misses::total 25926 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.inst 4879 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.inst 4062 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.inst 695 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.inst 300 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 995 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.inst 92450 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.inst 47410 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 139860 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 108557 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 57212 # number of demand (read+write) misses system.l2c.demand_misses::total 165786 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.inst 108557 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses system.l2c.overall_misses::cpu1.inst 57212 # number of overall misses system.l2c.overall_misses::total 165786 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 592000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 1134045250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 716250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 732959500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1868462500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.inst 8149146 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.inst 13619415 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 21768561 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 695470 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2181906 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 2877376 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.inst 6400503611 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.inst 3385304039 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 9785807650 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 592000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 7534548861 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 716250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 4118263539 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 11654270150 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 592000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 7534548861 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 716250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 4118263539 # number of overall miss cycles system.l2c.overall_miss_latency::total 11654270150 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 22278 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 6566 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 965251 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 22732 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 5189 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 969482 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1991498 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 575172 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 575172 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.inst 5833 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.inst 5088 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10921 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.inst 898 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.inst 394 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1292 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.inst 151106 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.inst 98118 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249224 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 22278 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 6566 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 1116357 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 22732 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 5189 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 1067600 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2240722 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 22278 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 6566 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 1116357 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 22732 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 5189 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 1067600 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2240722 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000305 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.016687 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.010111 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.836448 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.798349 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.818698 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.773942 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.761421 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.770124 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611822 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.inst 0.483194 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.561182 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000305 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.097242 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.053589 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.073988 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000305 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.097242 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.053589 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.073988 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70406.981437 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74776.525199 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 72069.061946 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1670.249231 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3352.884047 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 2434.689744 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1000.676259 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 7273.020000 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 2891.835176 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 69232.056366 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 71404.852120 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 69968.594666 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency system.l2c.demand_avg_miss_latency::total 70297.070621 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency system.l2c.overall_avg_miss_latency::total 70297.070621 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 66893 # number of writebacks system.l2c.writebacks::total 66893 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 16058 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 9780 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 25855 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4879 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4062 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 8941 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 695 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 300 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 995 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.inst 92450 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.inst 47410 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 139860 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 108508 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 57190 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 165715 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 108508 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 57190 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 165715 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 518500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 929504000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 609332000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 1540083250 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48881350 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 40684546 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 89565896 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6993689 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3002299 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 9995988 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5227989883 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2775821957 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 8003811840 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 518500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 6157493883 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 3385153957 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 9543895090 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 518500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 6157493883 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 3385153957 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 9543895090 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156449029487 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10979297747 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 167428327234 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364347483 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414886347 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 16779233830 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813376970 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 184207561064 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.toL2Bus.throughput 163445997 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 182407496 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) system.iobus.throughput 46024799 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution system.iobus.trans_dist::WriteReq 7966 # Transaction distribution system.iobus.trans_dist::WriteResp 7966 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 52721636 # Total data (bytes) system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.branchPred.lookups 6670288 # Number of BP lookups system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7193152 # DTB read hits system.cpu0.dtb.read_misses 17493 # DTB read misses system.cpu0.dtb.write_hits 6058571 # DTB write hits system.cpu0.dtb.write_misses 1416 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 7210645 # DTB read accesses system.cpu0.dtb.write_accesses 6059987 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 13251723 # DTB hits system.cpu0.dtb.misses 18909 # DTB misses system.cpu0.dtb.accesses 13270632 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.inst_hits 12268451 # ITB inst hits system.cpu0.itb.inst_misses 4809 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses system.cpu0.itb.hits 12268451 # DTB hits system.cpu0.itb.misses 4809 # DTB misses system.cpu0.itb.accesses 12273260 # DTB accesses system.cpu0.numCycles 431172708 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 29878954 # Number of instructions committed system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.cpi 14.430649 # CPI: cycles per instruction system.cpu0.ipc 0.069297 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed system.cpu0.tickCycles 351703818 # Number of cycles that the object actually ticked system.cpu0.idleCycles 79468890 # Total number of cycles that the object has spent stopped system.cpu0.icache.tags.replacements 775463 # number of replacements system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 13041458 # Number of tag accesses system.cpu0.icache.tags.data_accesses 13041458 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 11489502 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 11489502 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 11489502 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 11489502 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 11489502 # number of overall hits system.cpu0.icache.overall_hits::total 11489502 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 775978 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 775978 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 775978 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 775978 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 775978 # number of overall misses system.cpu0.icache.overall_misses::total 775978 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10689826155 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 10689826155 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 10689826155 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 10689826155 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 10689826155 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 10689826155 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 12265480 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 12265480 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 12265480 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 12265480 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 9133730845 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9133730845 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 9133730845 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9133730845 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 9133730845 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171407250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171407250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171407250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 171407250 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.063265 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.063265 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.063265 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 331184 # number of replacements system.cpu0.dcache.tags.tagsinuse 495.308279 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 11419092 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 331547 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 34.441850 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 235572250 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.308279 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967399 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.967399 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 363 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 48281639 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 48281639 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.inst 5587990 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 5587990 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.inst 5501455 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5501455 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152609 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 152609 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153662 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 153662 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.inst 11089445 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 11089445 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.inst 11089445 # number of overall hits system.cpu0.dcache.overall_hits::total 11089445 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.inst 255115 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 255115 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.inst 311930 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 311930 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8548 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8548 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7439 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7439 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.inst 567045 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 567045 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.inst 567045 # number of overall misses system.cpu0.dcache.overall_misses::total 567045 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3832963977 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 3832963977 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15354005377 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 15354005377 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89150250 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 89150250 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47371188 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 47371188 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.inst 19186969354 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 19186969354 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.inst 19186969354 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 19186969354 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.inst 5843105 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 5843105 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5813385 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5813385 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161157 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 161157 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161101 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 161101 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.inst 11656490 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 11656490 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.inst 11656490 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 11656490 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.043661 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.043661 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.053657 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.053657 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053041 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.048646 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.048646 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6367.951069 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks system.cpu0.dcache.writebacks::total 307170 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796523752 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796523752 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309645752 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309645752 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 6159330 # Number of BP lookups system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 6763605 # DTB read hits system.cpu1.dtb.read_misses 17087 # DTB read misses system.cpu1.dtb.write_hits 5563764 # DTB write hits system.cpu1.dtb.write_misses 2456 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 6780692 # DTB read accesses system.cpu1.dtb.write_accesses 5566220 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 12327369 # DTB hits system.cpu1.dtb.misses 19543 # DTB misses system.cpu1.dtb.accesses 12346912 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.inst_hits 11206823 # ITB inst hits system.cpu1.itb.inst_misses 4156 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses system.cpu1.itb.hits 11206823 # DTB hits system.cpu1.itb.misses 4156 # DTB misses system.cpu1.itb.accesses 11210979 # DTB accesses system.cpu1.numCycles 147611080 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 31966977 # Number of instructions committed system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.cpi 4.617611 # CPI: cycles per instruction system.cpu1.ipc 0.216562 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed system.cpu1.tickCycles 117794272 # Number of cycles that the object actually ticked system.cpu1.idleCycles 29816808 # Total number of cycles that the object has spent stopped system.cpu1.icache.tags.replacements 791766 # number of replacements system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits system.cpu1.icache.overall_hits::total 10411414 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses system.cpu1.icache.overall_misses::total 792279 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 11203693 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070716 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.070716 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070716 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.070716 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070716 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.070716 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 13387.462861 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 792279 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 792279 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 792279 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 792279 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 792279 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 792279 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9020137312 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 9020137312 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9020137312 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 9020137312 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9020137312 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 9020137312 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5771250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5771250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5771250 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5771250 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070716 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.070716 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 300206 # number of replacements system.cpu1.dcache.tags.tagsinuse 447.094079 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 10899911 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 300718 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 36.246287 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 76416861250 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.inst 447.094079 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.873231 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.873231 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 45736548 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 45736548 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.inst 6288103 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 6288103 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.inst 4421998 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 4421998 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78443 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 78443 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79055 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 79055 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.inst 10710101 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 10710101 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.inst 10710101 # number of overall hits system.cpu1.dcache.overall_hits::total 10710101 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.inst 241320 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 241320 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.inst 223635 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 223635 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10750 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 10750 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10087 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10087 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.inst 464955 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 464955 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.inst 464955 # number of overall misses system.cpu1.dcache.overall_misses::total 464955 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3586794993 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 3586794993 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8773828993 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 8773828993 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90116500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 90116500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50277799 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 50277799 # number of StoreCondReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.inst 12360623986 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 12360623986 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.inst 12360623986 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 12360623986 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6529423 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 6529423 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4645633 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 4645633 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89193 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 89193 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks system.cpu1.dcache.writebacks::total 268002 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36395 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98109 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 98109 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 34 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.inst 134504 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 134504 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.inst 134504 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 134504 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 204925 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082152 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082152 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.tags.tag_accesses 0 # Number of tag accesses system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------