sim_control.cc (12047:8b269268312c) sim_control.cc (12183:a097b7c2d9b6)
1/*
2 * Copyright (c) 2015, University of Kaiserslautern
3 * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:

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81 // register the systemc slave and master port handler
82 ExternalSlave::registerHandler("tlm_slave", new SCSlavePortHandler(*this));
83 ExternalMaster::registerHandler("tlm_master",
84 new SCMasterPortHandler(*this));
85
86 Trace::setDebugLogger(&logger);
87
88 Gem5SystemC::setTickFrequency();
1/*
2 * Copyright (c) 2015, University of Kaiserslautern
3 * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:

--- 72 unchanged lines hidden (view full) ---

81 // register the systemc slave and master port handler
82 ExternalSlave::registerHandler("tlm_slave", new SCSlavePortHandler(*this));
83 ExternalMaster::registerHandler("tlm_master",
84 new SCMasterPortHandler(*this));
85
86 Trace::setDebugLogger(&logger);
87
88 Gem5SystemC::setTickFrequency();
89 sc_core::sc_set_time_resolution(1, sc_core::SC_PS);
89 assert(sc_core::sc_get_time_resolution()
90 == sc_core::sc_time(1,sc_core::SC_PS));
90
91 Gem5SystemC::Module::setupEventQueues(*this);
92 initSignals();
93
94 Stats::initSimStats();
95 Stats::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
96
97 Trace::enable();

--- 126 unchanged lines hidden --- 		91
92 Gem5SystemC::Module::setupEventQueues(*this);
93 initSignals();
94
95 Stats::initSimStats();
96 Stats::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
97
98 Trace::enable();

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