SConscript (12047:8b269268312c) SConscript (13391:f298f7d04903)
1#!python
2
3# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met:

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33# Authors: Christian Menard
34
35Import('env')
36
37env = env.Clone()
38
39gem5_root = env['GEM5_ROOT']
40
1#!python
2
3# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met:

--- 24 unchanged lines hidden (view full) ---

33# Authors: Christian Menard
34
35Import('env')
36
37env = env.Clone()
38
39gem5_root = env['GEM5_ROOT']
40
41systemc_util_dir = gem5_root + '/util/systemc/gem5_within_systemc'
42
41systemc_src = []
43systemc_src = []
42systemc_src += Install('.', gem5_root + '/util/systemc/sc_gem5_control.cc'),
43systemc_src += Install('.', gem5_root + '/util/systemc/sc_logger.cc'),
44systemc_src += Install('.', gem5_root + '/util/systemc/sc_module.cc'),
45systemc_src += Install('.', gem5_root + '/util/systemc/stats.cc'),
44systemc_src += Install('.', systemc_util_dir + '/sc_gem5_control.cc'),
45systemc_src += Install('.', systemc_util_dir + '/sc_logger.cc'),
46systemc_src += Install('.', systemc_util_dir + '/sc_module.cc'),
47systemc_src += Install('.', systemc_util_dir + '/stats.cc'),
46
47tlm_src = []
48tlm_src += [File('master_transactor.cc')]
49tlm_src += [File('sc_ext.cc')]
50tlm_src += [File('sc_master_port.cc')]
51tlm_src += [File('sc_mm.cc')]
52tlm_src += [File('sc_slave_port.cc')]
53tlm_src += [File('sim_control.cc')]
54tlm_src += [File('slave_transactor.cc')]
55
56tlm = env.Library('gem5_tlm', tlm_src + systemc_src)
57
58Return('tlm')
48
49tlm_src = []
50tlm_src += [File('master_transactor.cc')]
51tlm_src += [File('sc_ext.cc')]
52tlm_src += [File('sc_master_port.cc')]
53tlm_src += [File('sc_mm.cc')]
54tlm_src += [File('sc_slave_port.cc')]
55tlm_src += [File('sim_control.cc')]
56tlm_src += [File('slave_transactor.cc')]
57
58tlm = env.Library('gem5_tlm', tlm_src + systemc_src)
59
60Return('tlm')