main.cc (11821:39b0a51c9e76) | main.cc (11822:9018cadf6c87) |
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1/* 2 * Copyright (c) 2015, University of Kaiserslautern 3 * Copyright (c) 2016, Dresden University of Technology (TU Dresden) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: --- 36 unchanged lines hidden (view full) --- 45 46#include <systemc> 47#include <tlm> 48 49#include "cli_parser.hh" 50#include "report_handler.hh" 51#include "sc_target.hh" 52#include "sim_control.hh" | 1/* 2 * Copyright (c) 2015, University of Kaiserslautern 3 * Copyright (c) 2016, Dresden University of Technology (TU Dresden) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: --- 36 unchanged lines hidden (view full) --- 45 46#include <systemc> 47#include <tlm> 48 49#include "cli_parser.hh" 50#include "report_handler.hh" 51#include "sc_target.hh" 52#include "sim_control.hh" |
53#include "slave_transactor.hh" |
|
53#include "stats.hh" 54 55int 56sc_main(int argc, char **argv) 57{ 58 CliParser parser; 59 parser.parse(argc, argv); 60 61 sc_core::sc_report_handler::set_handler(reportHandler); 62 | 54#include "stats.hh" 55 56int 57sc_main(int argc, char **argv) 58{ 59 CliParser parser; 60 parser.parse(argc, argv); 61 62 sc_core::sc_report_handler::set_handler(reportHandler); 63 |
63 Gem5SystemC::Gem5SimControl simControl("gem5", | 64 Gem5SystemC::Gem5SimControl sim_control("gem5", |
64 parser.getConfigFile(), 65 parser.getSimulationEnd(), 66 parser.getDebugFlags()); | 65 parser.getConfigFile(), 66 parser.getSimulationEnd(), 67 parser.getDebugFlags()); |
67 Target *memory; | |
68 69 unsigned long long int memorySize = 512*1024*1024ULL; 70 | 68 69 unsigned long long int memorySize = 512*1024*1024ULL; 70 |
71 tlm::tlm_initiator_socket <> *mem_port = 72 dynamic_cast<tlm::tlm_initiator_socket<> *>( 73 sc_core::sc_find_object("gem5.memory") 74 ); | 71 Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor"); 72 Target memory("memory", 73 parser.getVerboseFlag(), 74 memorySize, 75 parser.getMemoryOffset()); |
75 | 76 |
76 if (mem_port) { 77 SC_REPORT_INFO("sc_main", "Port Found"); 78 memory = new Target("memory", 79 parser.getVerboseFlag(), 80 memorySize, 81 parser.getMemoryOffset()); | 77 memory.socket.bind(transactor.socket); 78 transactor.sim_control.bind(sim_control); |
82 | 79 |
83 memory->socket.bind(*mem_port); 84 } else { 85 SC_REPORT_FATAL("sc_main", "Port Not Found"); 86 std::exit(EXIT_FAILURE); 87 } 88 | |
89 SC_REPORT_INFO("sc_main", "Start of Simulation"); 90 91 sc_core::sc_start(); 92 93 SC_REPORT_INFO("sc_main", "End of Simulation"); 94 95 CxxConfig::statsDump(); 96 97 return EXIT_SUCCESS; 98} | 80 SC_REPORT_INFO("sc_main", "Start of Simulation"); 81 82 sc_core::sc_start(); 83 84 SC_REPORT_INFO("sc_main", "End of Simulation"); 85 86 CxxConfig::statsDump(); 87 88 return EXIT_SUCCESS; 89} |