| README (11832:4d1f9823013a) | README (11971:9573d7d7811a) |
|---|---|
| 1This directory contains a demo of a coupling between gem5 and SystemC-TLM. It 2is based on the gem5-systemc implementation in utils/systemc. This Readme gives 3an overall overview (I), describes the source files in this directory (II), 4explains the build steps (III), shows how to run example simulations (IV-VI) 5and lists known issues (VII). 6 7 8I. Overview --- 15 unchanged lines hidden (view full) --- 24to the TLM world through target socket of the Gem5MasterTransactor. 25SCMasterPort and Gem5MasterTransactor are bound to each other by configuring 26them for the same port name. 27 28**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge. 29Gem5SlaveTransactor is a SystemC module that provides a initiator socket and 30represents the TLM end of the bridge. SCSlavePort implements gem5's 31ExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5 | 1This directory contains a demo of a coupling between gem5 and SystemC-TLM. It 2is based on the gem5-systemc implementation in utils/systemc. This Readme gives 3an overall overview (I), describes the source files in this directory (II), 4explains the build steps (III), shows how to run example simulations (IV-VI) 5and lists known issues (VII). 6 7 8I. Overview --- 15 unchanged lines hidden (view full) --- 24to the TLM world through target socket of the Gem5MasterTransactor. 25SCMasterPort and Gem5MasterTransactor are bound to each other by configuring 26them for the same port name. 27 28**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge. 29Gem5SlaveTransactor is a SystemC module that provides a initiator socket and 30represents the TLM end of the bridge. SCSlavePort implements gem5's 31ExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5 |
| 32requests send to the SCSlavePort, are translated to TLM requests and forwarded | 32requests sent to the SCSlavePort, are translated to TLM requests and forwarded |
| 33to the TLM world through the initiator socket of the Gem5SlaveTransactor. Then 34the TLM world handles the request and eventually issues a response. When the | 33to the TLM world through the initiator socket of the Gem5SlaveTransactor. Then 34the TLM world handles the request and eventually issues a response. When the |
| 35response arrives at the Gem5SlaveTransactor it gets translated back into a TLM 36response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort | 35response arrives at the Gem5SlaveTransactor it gets translated back into a 36gem5 response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort |
| 37and Gem5SlaveTransactor are bound to each other by configuring them for the 38same port name. 39 40**Gem5SimControl** is the central SystemC module that represents the complete 41gem5 world. It is responsible for instantiating all gem5 objects according to a 42given configuration file, for configuring the simulation and for maintaining 43the gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort 44and responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor --- 173 unchanged lines hidden --- | 37and Gem5SlaveTransactor are bound to each other by configuring them for the 38same port name. 39 40**Gem5SimControl** is the central SystemC module that represents the complete 41gem5 world. It is responsible for instantiating all gem5 objects according to a 42given configuration file, for configuring the simulation and for maintaining 43the gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort 44and responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor --- 173 unchanged lines hidden --- |