| o3_stat_config.ini (10016:dffa80408656) | o3_stat_config.ini (10354:2d6d7a056a38) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 26 unchanged lines hidden (view full) --- 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (O3CPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 26 unchanged lines hidden (view full) --- 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (O3CPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# |
| 43# icache = 44# icache.overall_hits::total 45# icache.overall_misses::total | 43# commit_inst_count = 44# system.cluster.cpu#.commit.committedInsts 45# system.cluster.cpu#.commit.commitSquashedInsts |
| 46# | 46# |
| 47# will display the icache as a stacked line chart. | 47# will display the inst counts (committed/squashed) as a stacked line chart. |
| 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] | 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] |
| 51# "system.cpu#." will automatically prepended for per-CPU stats | 51# '#' will be automatically replaced with the correct CPU id. |
| 52 53icache = | 52 53icache = |
| 54 icache.overall_hits::total 55 icache.overall_misses::total | 54 system.cluster.il1_cache#.overall_hits::total 55 system.cluster.il1_cache#.overall_misses::total |
| 56 57dcache = | 56 57dcache = |
| 58 dcache.overall_hits::total 59 dcache.overall_misses::total | 58 system.cluster.dl1_cache#.overall_hits::total 59 system.cluster.dl1_cache#.overall_misses::total |
| 60 | 60 |
| 61[PER_SWITCHCPU_STATS] 62# If starting from checkpoints, CPU stats will be kept in system.switch_cpus#. 63# structures. 64# "system.switch_cpus#" will automatically prepended for per-CPU stats. 65# Note: L1 caches and table walker caches will still be connected to 66# system.cpu#! 67 | |
| 68commit_inst_count = | 61commit_inst_count = |
| 69 commit.committedInsts 70 commit.commitSquashedInsts | 62 system.cluster.cpu#.commit.committedInsts 63 system.cluster.cpu#.commit.commitSquashedInsts |
| 71 72cycles = | 64 65cycles = |
| 73 numCycles 74 idleCycles | 66 system.cluster.cpu#.numCycles 67 system.cluster.cpu#.idleCycles |
| 75 76branch_mispredict = | 68 69branch_mispredict = |
| 77 commit.branchMispredicts 78 | 70 system.cluster.cpu#.commit.branchMispredicts |
| 79itb = | 71itb = |
| 80 itb.hits 81 itb.misses | 72 system.cluster.cpu#.itb.hits 73 system.cluster.cpu#.itb.misses |
| 82 83dtb = | 74 75dtb = |
| 84 dtb.hits 85 dtb.misses | 76 system.cluster.cpu#.dtb.hits 77 system.cluster.cpu#.dtb.misses |
| 86 87commit_inst_breakdown = | 78 79commit_inst_breakdown = |
| 88 commit.loads 89 commit.membars 90 commit.branches 91 commit.fp_insts 92 commit.int_insts | 80 system.cluster.cpu#.commit.loads 81 system.cluster.cpu#.commit.membars 82 system.cluster.cpu#.commit.branches 83 system.cluster.cpu#.commit.fp_insts 84 system.cluster.cpu#.commit.int_insts |
| 93 94int_regfile = | 85 86int_regfile = |
| 95 int_regfile_reads 96 int_regfile_writes | 87 system.cluster.cpu#.int_regfile_reads 88 system.cluster.cpu#.int_regfile_writes |
| 97 98misc_regfile = | 89 90misc_regfile = |
| 99 misc_regfile_reads 100 misc_regfile_writes | 91 system.cluster.cpu#.misc_regfile_reads 92 system.cluster.cpu#.misc_regfile_writes |
| 101 102rename_full = | 93 94rename_full = |
| 103 rename.ROBFullEvents 104 rename.IQFullEvents 105 rename.LSQFullEvents | 95 system.cluster.cpu#.rename.ROBFullEvents 96 system.cluster.cpu#.rename.IQFullEvents 97 system.cluster.cpu#.rename.LSQFullEvents |
| 106 107[PER_L2_STATS] | 98 99[PER_L2_STATS] |
| 108# Automatically adapts to how many l2 caches are in the system | 100# '#' will be automatically replaced with the correct L2 id. |
| 109 110l2_cache = | 101 102l2_cache = |
| 111 overall_hits::total 112 overall_misses::total | 103 system.cluster.l2_cache#.overall_hits::total 104 system.cluster.l2_cache#.overall_misses::total |
| 113 114[OTHER_STATS] 115# Anything that doesn't belong to CPU or L2 caches 116 117physmem = | 105 106[OTHER_STATS] 107# Anything that doesn't belong to CPU or L2 caches 108 109physmem = |
| 118 system.physmem.bytes_read::total 119 system.physmem.bytes_written::total | 110 system.memsys.mem_ctrls.bytes_read::total 111 system.memsys.mem_ctrls.bytes_written::total |