1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 27 unchanged lines hidden (view full) --- 36# Author: Dam Sunwoo 37# 38# Sample stats config file (O3CPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# 43# commit_inst_count = |
44# system.cpu#.commit.committedInsts 45# system.cpu#.commit.commitSquashedInsts |
46# 47# will display the inst counts (committed/squashed) as a stacked line chart. 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] 51# '#' will be automatically replaced with the correct CPU id. 52 53icache = |
54 system.il1_cache#.overall_hits::total 55 system.il1_cache#.overall_misses::total |
56 57dcache = |
58 system.dl1_cache#.overall_hits::total 59 system.dl1_cache#.overall_misses::total |
60 61commit_inst_count = |
62 system.cpu#.commit.committedInsts 63 system.cpu#.commit.commitSquashedInsts |
64 65cycles = |
66 system.cpu#.numCycles 67 system.cpu#.idleCycles |
68 69branch_mispredict = |
70 system.cpu#.commit.branchMispredicts |
71itb = |
72 system.cpu#.itb.hits 73 system.cpu#.itb.misses |
74 75dtb = |
76 system.cpu#.dtb.hits 77 system.cpu#.dtb.misses |
78 79commit_inst_breakdown = |
80 system.cpu#.commit.loads 81 system.cpu#.commit.membars 82 system.cpu#.commit.branches 83 system.cpu#.commit.fp_insts 84 system.cpu#.commit.int_insts |
85 86int_regfile = |
87 system.cpu#.int_regfile_reads 88 system.cpu#.int_regfile_writes |
89 90misc_regfile = |
91 system.cpu#.misc_regfile_reads 92 system.cpu#.misc_regfile_writes |
93 94rename_full = |
95 system.cpu#.rename.ROBFullEvents 96 system.cpu#.rename.IQFullEvents 97 system.cpu#.rename.LSQFullEvents |
98 99[PER_L2_STATS] 100# '#' will be automatically replaced with the correct L2 id. 101 102l2_cache = |
103 system.l2_cache#.overall_hits::total 104 system.l2_cache#.overall_misses::total |
105 106[OTHER_STATS] 107# Anything that doesn't belong to CPU or L2 caches 108 109physmem = 110 system.memsys.mem_ctrls.bytes_read::total 111 system.memsys.mem_ctrls.bytes_written::total |