1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (O3CPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# 43# commit_inst_count =
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (O3CPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# 43# commit_inst_count =
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44# system.cluster.cpu#.commit.committedInsts 45# system.cluster.cpu#.commit.commitSquashedInsts
| 44# system.cpu#.commit.committedInsts 45# system.cpu#.commit.commitSquashedInsts
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46# 47# will display the inst counts (committed/squashed) as a stacked line chart. 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] 51# '#' will be automatically replaced with the correct CPU id. 52 53icache =
| 46# 47# will display the inst counts (committed/squashed) as a stacked line chart. 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] 51# '#' will be automatically replaced with the correct CPU id. 52 53icache =
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54 system.cluster.il1_cache#.overall_hits::total 55 system.cluster.il1_cache#.overall_misses::total
| 54 system.il1_cache#.overall_hits::total 55 system.il1_cache#.overall_misses::total
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56 57dcache =
| 56 57dcache =
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58 system.cluster.dl1_cache#.overall_hits::total 59 system.cluster.dl1_cache#.overall_misses::total
| 58 system.dl1_cache#.overall_hits::total 59 system.dl1_cache#.overall_misses::total
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60 61commit_inst_count =
| 60 61commit_inst_count =
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62 system.cluster.cpu#.commit.committedInsts 63 system.cluster.cpu#.commit.commitSquashedInsts
| 62 system.cpu#.commit.committedInsts 63 system.cpu#.commit.commitSquashedInsts
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64 65cycles =
| 64 65cycles =
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66 system.cluster.cpu#.numCycles 67 system.cluster.cpu#.idleCycles
| 66 system.cpu#.numCycles 67 system.cpu#.idleCycles
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68 69branch_mispredict =
| 68 69branch_mispredict =
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70 system.cluster.cpu#.commit.branchMispredicts
| 70 system.cpu#.commit.branchMispredicts
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71itb =
| 71itb =
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72 system.cluster.cpu#.itb.hits 73 system.cluster.cpu#.itb.misses
| 72 system.cpu#.itb.hits 73 system.cpu#.itb.misses
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74 75dtb =
| 74 75dtb =
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76 system.cluster.cpu#.dtb.hits 77 system.cluster.cpu#.dtb.misses
| 76 system.cpu#.dtb.hits 77 system.cpu#.dtb.misses
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78 79commit_inst_breakdown =
| 78 79commit_inst_breakdown =
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80 system.cluster.cpu#.commit.loads 81 system.cluster.cpu#.commit.membars 82 system.cluster.cpu#.commit.branches 83 system.cluster.cpu#.commit.fp_insts 84 system.cluster.cpu#.commit.int_insts
| 80 system.cpu#.commit.loads 81 system.cpu#.commit.membars 82 system.cpu#.commit.branches 83 system.cpu#.commit.fp_insts 84 system.cpu#.commit.int_insts
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85 86int_regfile =
| 85 86int_regfile =
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87 system.cluster.cpu#.int_regfile_reads 88 system.cluster.cpu#.int_regfile_writes
| 87 system.cpu#.int_regfile_reads 88 system.cpu#.int_regfile_writes
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89 90misc_regfile =
| 89 90misc_regfile =
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91 system.cluster.cpu#.misc_regfile_reads 92 system.cluster.cpu#.misc_regfile_writes
| 91 system.cpu#.misc_regfile_reads 92 system.cpu#.misc_regfile_writes
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93 94rename_full =
| 93 94rename_full =
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95 system.cluster.cpu#.rename.ROBFullEvents 96 system.cluster.cpu#.rename.IQFullEvents 97 system.cluster.cpu#.rename.LSQFullEvents
| 95 system.cpu#.rename.ROBFullEvents 96 system.cpu#.rename.IQFullEvents 97 system.cpu#.rename.LSQFullEvents
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98 99[PER_L2_STATS] 100# '#' will be automatically replaced with the correct L2 id. 101 102l2_cache =
| 98 99[PER_L2_STATS] 100# '#' will be automatically replaced with the correct L2 id. 101 102l2_cache =
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103 system.cluster.l2_cache#.overall_hits::total 104 system.cluster.l2_cache#.overall_misses::total
| 103 system.l2_cache#.overall_hits::total 104 system.l2_cache#.overall_misses::total
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105 106[OTHER_STATS] 107# Anything that doesn't belong to CPU or L2 caches 108 109physmem = 110 system.memsys.mem_ctrls.bytes_read::total 111 system.memsys.mem_ctrls.bytes_written::total
| 105 106[OTHER_STATS] 107# Anything that doesn't belong to CPU or L2 caches 108 109physmem = 110 system.memsys.mem_ctrls.bytes_read::total 111 system.memsys.mem_ctrls.bytes_written::total
|