| m5op_sparc.S (12157:c27b548bad70) | m5op_sparc.S (12160:c282cb504275) |
|---|---|
| 1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 M5EXIT 60END(m5_exit) 61 62LEAF(m5_panic) 63 retl 64 PANIC 65END(m5_panic) 66 | 1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 M5EXIT 60END(m5_exit) 61 62LEAF(m5_panic) 63 retl 64 PANIC 65END(m5_panic) 66 |
| 67LEAF(m5_readfile) | 67LEAF(m5_read_file) |
| 68 retl 69 READFILE | 68 retl 69 READFILE |
| 70END(m5_readfile) | 70END(m5_read_file) |
| 71 | 71 |
| 72LEAF(m5_debugbreak) | 72LEAF(m5_debug_break) |
| 73 retl 74 DEBUGBREAK | 73 retl 74 DEBUGBREAK |
| 75END(m5_debugbreak) | 75END(m5_debug_break) |
| 76 77/* !!!!!! All code below here just panics !!!!!! */ | 76 77/* !!!!!! All code below here just panics !!!!!! */ |
| 78LEAF(arm) | 78LEAF(m5_arm) |
| 79 retl 80 PANIC | 79 retl 80 PANIC |
| 81END(arm) | 81END(m5_arm) |
| 82 | 82 |
| 83LEAF(quiesce) | 83LEAF(m5_quiesce) |
| 84 retl 85 PANIC | 84 retl 85 PANIC |
| 86END(quiesce) | 86END(m5_quiesce) |
| 87 | 87 |
| 88LEAF(quiesceNs) | 88LEAF(m5_quiesce_ns) |
| 89 retl 90 PANIC | 89 retl 90 PANIC |
| 91END(quiesceNs) | 91END(m5_quiesce_ns) |
| 92 | 92 |
| 93LEAF(quiesceCycle) | 93LEAF(m5_quiesce_cycle) |
| 94 retl 95 PANIC | 94 retl 95 PANIC |
| 96END(quiesceCycle) | 96END(m5_quiesce_cycle) |
| 97 | 97 |
| 98LEAF(quiesceTime) | 98LEAF(m5_quiesce_time) |
| 99 retl 100 PANIC | 99 retl 100 PANIC |
| 101END(quiesceTime) | 101END(m5_quiesce_time) |
| 102 | 102 |
| 103LEAF(m5_initparam) | 103LEAF(m5_init_param) |
| 104 retl 105 PANIC | 104 retl 105 PANIC |
| 106END(m5_initparam) | 106END(m5_init_param) |
| 107 | 107 |
| 108LEAF(m5_loadsymbol) | 108LEAF(m5_load_symbol) |
| 109 retl 110 PANIC | 109 retl 110 PANIC |
| 111END(m5_loadsymbol) | 111END(m5_load_symbol) |
| 112 113LEAF(m5_reset_stats) 114 retl 115 PANIC 116END(m5_reset_stats) 117 118LEAF(m5_dump_stats) 119 retl 120 PANIC 121END(m5_dump_stats) 122 | 112 113LEAF(m5_reset_stats) 114 retl 115 PANIC 116END(m5_reset_stats) 117 118LEAF(m5_dump_stats) 119 retl 120 PANIC 121END(m5_dump_stats) 122 |
| 123LEAF(m5_dumpreset_stats) | 123LEAF(m5_dump_reset_stats) |
| 124 retl 125 PANIC | 124 retl 125 PANIC |
| 126END(m5_dumpreset_stats) | 126END(m5_dump_reset_stats) |
| 127 128LEAF(m5_checkpoint) 129 retl 130 PANIC 131END(m5_checkpoint) 132 | 127 128LEAF(m5_checkpoint) 129 retl 130 PANIC 131END(m5_checkpoint) 132 |
| 133LEAF(m5_switchcpu) | 133LEAF(m5_switch_cpu) |
| 134 retl 135 PANIC | 134 retl 135 PANIC |
| 136END(m5_switchcpu) | 136END(m5_switch_cpu) |
| 137 | 137 |
| 138LEAF(m5_addsymbol) | 138LEAF(m5_add_symbol) |
| 139 retl 140 PANIC | 139 retl 140 PANIC |
| 141END(m5_addsymbol) | 141END(m5_add_symbol) |
| 142 143LEAF(m5_anbegin) 144 retl 145 PANIC 146END(m5_anbegin) 147 148LEAF(m5_anwait) 149 retl 150 PANIC 151END(m5_anwait) 152 153 | 142 143LEAF(m5_anbegin) 144 retl 145 PANIC 146END(m5_anbegin) 147 148LEAF(m5_anwait) 149 retl 150 PANIC 151END(m5_anwait) 152 153 |