1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 * Ali Saidi
42 * Chander Sudanthi
43 */
44
45#define m5_op 0xFF
46
47#include "m5ops.h"
48
49#define INST(op, ra, rb, func) \
50 .long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
51/* m5ops m5func ra coproc 1 op=1 rb */
52
53#define LEAF(func) \
54 .globl func; \
55func:
56
57#define RET \
58 RET
59
60#define END(func) \
61
62#define SIMPLE_OP(_f, _o) \
63 LEAF(_f) \
64 _o; \
65 RET; \
66 END(_f)
67
68#define ARM INST(m5_op, 0, 0, arm_func)
69#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
70#define QUIESCENS INST(m5_op, 0, 0, quiescens_func)
71#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func)
72#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
73#define RPNS INST(m5_op, 0, 0, rpns_func)
74#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func)
75#define M5EXIT INST(m5_op, 0, 0, exit_func)
| 1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 * Ali Saidi
42 * Chander Sudanthi
43 */
44
45#define m5_op 0xFF
46
47#include "m5ops.h"
48
49#define INST(op, ra, rb, func) \
50 .long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
51/* m5ops m5func ra coproc 1 op=1 rb */
52
53#define LEAF(func) \
54 .globl func; \
55func:
56
57#define RET \
58 RET
59
60#define END(func) \
61
62#define SIMPLE_OP(_f, _o) \
63 LEAF(_f) \
64 _o; \
65 RET; \
66 END(_f)
67
68#define ARM INST(m5_op, 0, 0, arm_func)
69#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
70#define QUIESCENS INST(m5_op, 0, 0, quiescens_func)
71#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func)
72#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
73#define RPNS INST(m5_op, 0, 0, rpns_func)
74#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func)
75#define M5EXIT INST(m5_op, 0, 0, exit_func)
|
76#define INITPARAM INST(m5_op, 0, 0, initparam_func)
77#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func)
78#define RESET_STATS INST(m5_op, 0, 0, resetstats_func)
79#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func)
80#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func)
81#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func)
82#define READFILE INST(m5_op, 0, 0, readfile_func)
83#define WRITEFILE INST(m5_op, 0, 0, writefile_func)
84#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
85#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
86#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func)
87#define PANIC INST(m5_op, 0, 0, panic_func)
88#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func)
89#define WORK_END INST(m5_op, 0, 0, work_end_func)
90
91#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
92#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
93#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func)
94#define AN_END INST(m5_op, an_end, 0, annotate_func)
95#define AN_Q INST(m5_op, an_q, 0, annotate_func)
96#define AN_RQ INST(m5_op, an_rq, 0, annotate_func)
97#define AN_DQ INST(m5_op, an_dq, 0, annotate_func)
98#define AN_WF INST(m5_op, an_wf, 0, annotate_func)
99#define AN_WE INST(m5_op, an_we, 0, annotate_func)
100#define AN_WS INST(m5_op, an_ws, 0, annotate_func)
101#define AN_SQ INST(m5_op, an_sq, 0, annotate_func)
102#define AN_AQ INST(m5_op, an_aq, 0, annotate_func)
103#define AN_PQ INST(m5_op, an_pq, 0, annotate_func)
104#define AN_L INST(m5_op, an_l, 0, annotate_func)
105#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func)
106#define AN_GETID INST(m5_op, an_getid, 0, annotate_func)
107
108.text
109
110SIMPLE_OP(arm, ARM)
111SIMPLE_OP(quiesce, QUIESCE)
112SIMPLE_OP(quiesceNs, QUIESCENS)
113SIMPLE_OP(quiesceCycle, QUIESCECYC)
114SIMPLE_OP(quiesceTime, QUIESCETIME)
115SIMPLE_OP(rpns, RPNS)
116SIMPLE_OP(wakeCPU, WAKE_CPU)
117SIMPLE_OP(m5_exit, M5EXIT)
| 77#define INITPARAM INST(m5_op, 0, 0, initparam_func)
78#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func)
79#define RESET_STATS INST(m5_op, 0, 0, resetstats_func)
80#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func)
81#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func)
82#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func)
83#define READFILE INST(m5_op, 0, 0, readfile_func)
84#define WRITEFILE INST(m5_op, 0, 0, writefile_func)
85#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
86#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
87#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func)
88#define PANIC INST(m5_op, 0, 0, panic_func)
89#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func)
90#define WORK_END INST(m5_op, 0, 0, work_end_func)
91
92#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
93#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
94#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func)
95#define AN_END INST(m5_op, an_end, 0, annotate_func)
96#define AN_Q INST(m5_op, an_q, 0, annotate_func)
97#define AN_RQ INST(m5_op, an_rq, 0, annotate_func)
98#define AN_DQ INST(m5_op, an_dq, 0, annotate_func)
99#define AN_WF INST(m5_op, an_wf, 0, annotate_func)
100#define AN_WE INST(m5_op, an_we, 0, annotate_func)
101#define AN_WS INST(m5_op, an_ws, 0, annotate_func)
102#define AN_SQ INST(m5_op, an_sq, 0, annotate_func)
103#define AN_AQ INST(m5_op, an_aq, 0, annotate_func)
104#define AN_PQ INST(m5_op, an_pq, 0, annotate_func)
105#define AN_L INST(m5_op, an_l, 0, annotate_func)
106#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func)
107#define AN_GETID INST(m5_op, an_getid, 0, annotate_func)
108
109.text
110
111SIMPLE_OP(arm, ARM)
112SIMPLE_OP(quiesce, QUIESCE)
113SIMPLE_OP(quiesceNs, QUIESCENS)
114SIMPLE_OP(quiesceCycle, QUIESCECYC)
115SIMPLE_OP(quiesceTime, QUIESCETIME)
116SIMPLE_OP(rpns, RPNS)
117SIMPLE_OP(wakeCPU, WAKE_CPU)
118SIMPLE_OP(m5_exit, M5EXIT)
|
118SIMPLE_OP(m5_initparam, INITPARAM)
119SIMPLE_OP(m5_loadsymbol, LOADSYMBOL)
120SIMPLE_OP(m5_reset_stats, RESET_STATS)
121SIMPLE_OP(m5_dump_stats, DUMP_STATS)
122SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS)
123SIMPLE_OP(m5_checkpoint, CHECKPOINT)
124SIMPLE_OP(m5_readfile, READFILE)
125SIMPLE_OP(m5_writefile, WRITEFILE)
126SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
127SIMPLE_OP(m5_switchcpu, SWITCHCPU)
128SIMPLE_OP(m5_addsymbol, ADDSYMBOL)
129SIMPLE_OP(m5_panic, PANIC)
130SIMPLE_OP(m5_work_begin, WORK_BEGIN)
131SIMPLE_OP(m5_work_end, WORK_END)
132
133SIMPLE_OP(m5a_bsm, AN_BSM)
134SIMPLE_OP(m5a_esm, AN_ESM)
135SIMPLE_OP(m5a_begin, AN_BEGIN)
136SIMPLE_OP(m5a_end, AN_END)
137SIMPLE_OP(m5a_q, AN_Q)
138SIMPLE_OP(m5a_rq, AN_RQ)
139SIMPLE_OP(m5a_dq, AN_DQ)
140SIMPLE_OP(m5a_wf, AN_WF)
141SIMPLE_OP(m5a_we, AN_WE)
142SIMPLE_OP(m5a_ws, AN_WS)
143SIMPLE_OP(m5a_sq, AN_SQ)
144SIMPLE_OP(m5a_aq, AN_AQ)
145SIMPLE_OP(m5a_pq, AN_PQ)
146SIMPLE_OP(m5a_l, AN_L)
147SIMPLE_OP(m5a_identify, AN_IDENTIFY)
148SIMPLE_OP(m5a_getid, AN_GETID)
149
| 120SIMPLE_OP(m5_initparam, INITPARAM)
121SIMPLE_OP(m5_loadsymbol, LOADSYMBOL)
122SIMPLE_OP(m5_reset_stats, RESET_STATS)
123SIMPLE_OP(m5_dump_stats, DUMP_STATS)
124SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS)
125SIMPLE_OP(m5_checkpoint, CHECKPOINT)
126SIMPLE_OP(m5_readfile, READFILE)
127SIMPLE_OP(m5_writefile, WRITEFILE)
128SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
129SIMPLE_OP(m5_switchcpu, SWITCHCPU)
130SIMPLE_OP(m5_addsymbol, ADDSYMBOL)
131SIMPLE_OP(m5_panic, PANIC)
132SIMPLE_OP(m5_work_begin, WORK_BEGIN)
133SIMPLE_OP(m5_work_end, WORK_END)
134
135SIMPLE_OP(m5a_bsm, AN_BSM)
136SIMPLE_OP(m5a_esm, AN_ESM)
137SIMPLE_OP(m5a_begin, AN_BEGIN)
138SIMPLE_OP(m5a_end, AN_END)
139SIMPLE_OP(m5a_q, AN_Q)
140SIMPLE_OP(m5a_rq, AN_RQ)
141SIMPLE_OP(m5a_dq, AN_DQ)
142SIMPLE_OP(m5a_wf, AN_WF)
143SIMPLE_OP(m5a_we, AN_WE)
144SIMPLE_OP(m5a_ws, AN_WS)
145SIMPLE_OP(m5a_sq, AN_SQ)
146SIMPLE_OP(m5a_aq, AN_AQ)
147SIMPLE_OP(m5a_pq, AN_PQ)
148SIMPLE_OP(m5a_l, AN_L)
149SIMPLE_OP(m5a_identify, AN_IDENTIFY)
150SIMPLE_OP(m5a_getid, AN_GETID)
151
|