| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.250987 # Number of seconds simulated 4sim_ticks 250987138500 # Number of ticks simulated 5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.250992 # Number of seconds simulated 4sim_ticks 250991873500 # Number of ticks simulated 5final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 493662 # Simulator instruction rate (inst/s) 8host_op_rate 827423 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 938152393 # Simulator tick rate (ticks/s) 10host_mem_usage 294200 # Number of bytes of host memory used 11host_seconds 267.53 # Real time elapsed on the host | 7host_inst_rate 1054537 # Simulator instruction rate (inst/s) 8host_op_rate 1767501 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2004072574 # Simulator tick rate (ticks/s) 10host_mem_usage 299608 # Number of bytes of host memory used 11host_seconds 125.24 # Real time elapsed on the host |
| 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 19system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 19system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 25system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 34system.cpu_clk_domain.clock 500 # Clock period in ticks | 34system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 39system.cpu.workload.num_syscalls 400 # Number of system calls | 39system.cpu.workload.num_syscalls 400 # Number of system calls |
| 40system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states 41system.cpu.numCycles 501974277 # number of cpu cycles simulated | 40system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states 41system.cpu.numCycles 501983747 # number of cpu cycles simulated |
| 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 132071193 # Number of instructions committed 45system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 48system.cpu.num_func_calls 1595632 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 54system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written 56system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read 57system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written 58system.cpu.num_mem_refs 77165304 # number of memory refs 59system.cpu.num_load_insts 56649587 # Number of load instructions 60system.cpu.num_store_insts 20515717 # Number of store instructions 61system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 132071193 # Number of instructions committed 45system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 48system.cpu.num_func_calls 1595632 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 54system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written 56system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read 57system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written 58system.cpu.num_mem_refs 77165304 # number of memory refs 59system.cpu.num_load_insts 56649587 # Number of load instructions 60system.cpu.num_store_insts 20515717 # Number of store instructions 61system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 62system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles | 62system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles |
| 63system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 65system.cpu.Branches 12326938 # Number of branches fetched 66system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction 67system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction 68system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction 69system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction 70system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 93system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 96system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 97system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 221363385 # Class of executed instruction | 63system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 65system.cpu.Branches 12326938 # Number of branches fetched 66system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction 67system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction 68system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction 69system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction 70system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 93system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 96system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 97system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 221363385 # Class of executed instruction |
| 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 102system.cpu.dcache.tags.replacements 41 # number of replacements | 102system.cpu.dcache.tags.replacements 41 # number of replacements |
| 103system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use | 103system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use |
| 104system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 104system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 108system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy | 108system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy |
| 111system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses | 111system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses |
| 120system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 120system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 121system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits 122system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits 123system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits 124system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits 125system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits 126system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits 127system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits 128system.cpu.dcache.overall_hits::total 77195831 # number of overall hits 129system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses 130system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses 131system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses 132system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses 133system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses 134system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses 135system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses 136system.cpu.dcache.overall_misses::total 1905 # number of overall misses | 121system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits 122system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits 123system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits 124system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits 125system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits 126system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits 127system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits 128system.cpu.dcache.overall_hits::total 77195831 # number of overall hits 129system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses 130system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses 131system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses 132system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses 133system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses 134system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses 135system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses 136system.cpu.dcache.overall_misses::total 1905 # number of overall misses |
| 137system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles 138system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles 141system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles | 137system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles 138system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles 141system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles |
| 145system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses 150system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses 151system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses 152system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses 153system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses 154system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 155system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses 156system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses 157system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 158system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 159system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 160system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses | 145system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses 150system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses 151system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses 152system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses 153system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses 154system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 155system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses 156system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses 157system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 158system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 159system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 160system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses |
| 161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency 162system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency 164system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency 166system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency | 161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency 162system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency 164system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency 165system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency 166system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency |
| 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.dcache.writebacks::writebacks 7 # number of writebacks 176system.cpu.dcache.writebacks::total 7 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses 181system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses 182system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses 183system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses 184system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses | 169system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.dcache.writebacks::writebacks 7 # number of writebacks 176system.cpu.dcache.writebacks::total 7 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses 181system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses 182system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses 183system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses 184system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses |
| 185system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles | 185system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles |
| 193system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 198system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 199system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 200system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses | 193system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 198system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 199system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 200system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses |
| 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 209system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency 209system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 210system.cpu.icache.tags.replacements 2836 # number of replacements | 210system.cpu.icache.tags.replacements 2836 # number of replacements |
| 211system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use | 211system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use |
| 212system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 212system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 216system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor 217system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy | 216system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor 217system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy |
| 219system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id | 219system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id |
| 222system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 223system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id | 222system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id 223system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id |
| 224system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 225system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id 226system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses 227system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses | 224system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 225system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id 226system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses 227system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses |
| 228system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 228system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 229system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits 230system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits 231system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits 232system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits 233system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 234system.cpu.icache.overall_hits::total 173489673 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses 237system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses 238system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses 239system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses 240system.cpu.icache.overall_misses::total 4694 # number of overall misses | 229system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits 230system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits 231system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits 232system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits 233system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 234system.cpu.icache.overall_hits::total 173489673 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses 237system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses 238system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses 239system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses 240system.cpu.icache.overall_misses::total 4694 # number of overall misses |
| 241system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles 242system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles 243system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles 244system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles 245system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles 246system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles | 241system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles 242system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles 243system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles 244system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles 245system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles 246system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles |
| 247system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) 248system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) 249system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses 250system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses 251system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses 252system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses 253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 254system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses 255system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses 256system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 257system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses 258system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses | 247system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) 248system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) 249system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses 250system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses 251system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses 252system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses 253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 254system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses 255system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses 256system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 257system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses 258system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses |
| 259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency 261system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency 262system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency | 259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency 261system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency 262system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency |
| 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 271system.cpu.icache.writebacks::writebacks 2836 # number of writebacks 272system.cpu.icache.writebacks::total 2836 # number of writebacks 273system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 275system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 276system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 277system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 278system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses | 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 271system.cpu.icache.writebacks::writebacks 2836 # number of writebacks 272system.cpu.icache.writebacks::total 2836 # number of writebacks 273system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 275system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 276system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 277system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 278system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses |
| 279system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles 280system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles 281system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles 282system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles 283system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles 284system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles | 279system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles 280system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles 281system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles 282system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles 283system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles 284system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles |
| 285system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses 286system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses 287system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 288system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 285system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses 286system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses 287system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 288system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 297system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency 297system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 298system.cpu.l2cache.tags.replacements 0 # number of replacements | 298system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 299system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use 300system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. | 299system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use 300system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks. |
| 303system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 303system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 304system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor 306system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor 307system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy | 304system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor |
| 308system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy | 306system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy |
| 309system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy 310system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy 311system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id 315system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id 316system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id 317system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id 318system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses 319system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses 320system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 307system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy 309system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id 315system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id 316system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses 317system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses 318system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 321system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits 322system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits 323system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits 324system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits 325system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits 326system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits 327system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits 328system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 341system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses 342system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses 343system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses 344system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses 345system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses 346system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses 347system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses 348system.cpu.l2cache.overall_misses::total 4735 # number of overall misses | 319system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits 320system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits 321system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits 322system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits 323system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits 324system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits 325system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits 326system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 339system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses 340system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses 341system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses 342system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses 343system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses 344system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses 345system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses 346system.cpu.l2cache.overall_misses::total 4735 # number of overall misses |
| 349system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles 350system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles 351system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles 352system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles 353system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles 354system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles 355system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles 356system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles 357system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles 358system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles 359system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles 360system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles | 347system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles 348system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles 349system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles 350system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles 351system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles 352system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles 353system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles 354system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles 355system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles 356system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles 357system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles 358system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles |
| 361system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) 362system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) 363system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) 364system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) 365system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) 366system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) 367system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) 368system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 381system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses 382system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses 383system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses 384system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses 385system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses 386system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses 387system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses 388system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses | 359system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) 360system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) 361system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) 362system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) 363system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) 364system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) 365system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) 366system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 379system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses 380system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses 381system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses 382system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses 383system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses 384system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses 385system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses 386system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses |
| 389system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency 390system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency 391system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency 392system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency 393system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency 394system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency 395system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency 396system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency 397system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency 398system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency 399system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency 400system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency | 387system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency 388system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency 389system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency 390system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency 391system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency 392system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency 393system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency 394system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency 395system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency 396system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency 397system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency 398system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency |
| 401system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses 408system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses 409system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses 410system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses 411system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses 412system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses 413system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses 414system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses 415system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses 416system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses 417system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses 418system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses | 399system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 400system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 402system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 403system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 404system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses 406system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses 407system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses 408system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses 409system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses 410system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses 411system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses 412system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses 413system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses 414system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses 415system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses 416system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses |
| 419system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles 420system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles 421system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles 422system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles 423system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles 424system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles 425system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles 426system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles 427system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles 428system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles 429system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles 430system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles | 417system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles 418system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles 419system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles 420system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles 421system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles 422system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles 423system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles 424system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles 425system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles 426system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles 427system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles 428system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles |
| 431system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses 432system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses 433system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses 434system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses 435system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses 436system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses 437system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses 438system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses 439system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses 440system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses 441system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses 442system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses | 429system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses 430system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses 431system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses 432system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses 433system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses 434system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses 435system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses 436system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses 437system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses 438system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses 439system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses 440system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses |
| 443system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency 444system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency 445system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency 446system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency 447system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency 448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency 449system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 452system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency | 441system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency 442system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency 443system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency 444system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency 445system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency 446system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency 448system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency 449system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency 451system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency 452system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency |
| 455system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 453system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 454system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 455system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 456system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 457system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 458system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 461system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 459system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 462system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 487system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram 489system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) 490system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 491system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 492system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 493system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 494system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 460system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 485system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram 487system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) 488system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 489system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 490system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 491system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 492system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 495system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states | 493system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter. 494system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 495system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 496system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 497system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 498system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 499system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states |
| 496system.membus.trans_dist::ReadResp 3160 # Transaction distribution 497system.membus.trans_dist::ReadExReq 1575 # Transaction distribution 498system.membus.trans_dist::ReadExResp 1575 # Transaction distribution 499system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution 500system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) 501system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) 502system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) 503system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 500system.membus.trans_dist::ReadResp 3160 # Transaction distribution 501system.membus.trans_dist::ReadExReq 1575 # Transaction distribution 502system.membus.trans_dist::ReadExResp 1575 # Transaction distribution 503system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution 504system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) 505system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) 506system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) 507system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) --- 20 unchanged lines hidden --- |