| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250987 # Number of seconds simulated 4sim_ticks 250987138500 # Number of ticks simulated 5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250987 # Number of seconds simulated 4sim_ticks 250987138500 # Number of ticks simulated 5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 489633 # Simulator instruction rate (inst/s) 8host_op_rate 820669 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 930494730 # Simulator tick rate (ticks/s) 10host_mem_usage 293244 # Number of bytes of host memory used 11host_seconds 269.74 # Real time elapsed on the host | 7host_inst_rate 1028477 # Simulator instruction rate (inst/s) 8host_op_rate 1723822 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1954510825 # Simulator tick rate (ticks/s) 10host_mem_usage 341680 # Number of bytes of host memory used 11host_seconds 128.41 # Real time elapsed on the host |
| 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 19system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks | 34system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 34system.cpu.workload.num_syscalls 400 # Number of system calls | 39system.cpu.workload.num_syscalls 400 # Number of system calls |
| 40system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states |
|
| 35system.cpu.numCycles 501974277 # number of cpu cycles simulated 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 132071193 # Number of instructions committed 39system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 42system.cpu.num_func_calls 1595632 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 90system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 91system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 221363385 # Class of executed instruction | 41system.cpu.numCycles 501974277 # number of cpu cycles simulated 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 132071193 # Number of instructions committed 45system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 48system.cpu.num_func_calls 1595632 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 93system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 96system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 97system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 221363385 # Class of executed instruction |
| 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 95system.cpu.dcache.tags.replacements 41 # number of replacements 96system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use 97system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor 102system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id 110system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id 111system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses 112system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses | 102system.cpu.dcache.tags.replacements 41 # number of replacements 103system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses |
| 120system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 113system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits 114system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits 115system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits 116system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits 117system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits 118system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits 119system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits 120system.cpu.dcache.overall_hits::total 77195831 # number of overall hits --- 72 unchanged lines hidden (view full) --- 193system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency 194system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency 195system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency 196system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency 197system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 198system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 199system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 200system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency | 121system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits 122system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits 123system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits 124system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits 125system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits 126system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits 127system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits 128system.cpu.dcache.overall_hits::total 77195831 # number of overall hits --- 72 unchanged lines hidden (view full) --- 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency |
| 209system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 201system.cpu.icache.tags.replacements 2836 # number of replacements 202system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy 210system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 212system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 216system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id 217system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses 218system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses | 210system.cpu.icache.tags.replacements 2836 # number of replacements 211system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use 212system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor 217system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 223system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id 224system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 225system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id 226system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses 227system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses |
| 228system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 219system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits 220system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits 221system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits 222system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits 223system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 224system.cpu.icache.overall_hits::total 173489673 # number of overall hits 225system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 226system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency | 229system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits 230system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits 231system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits 232system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits 233system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 234system.cpu.icache.overall_hits::total 173489673 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency |
| 297system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 287system.cpu.l2cache.tags.replacements 0 # number of replacements 288system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use 289system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 290system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 291system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 292system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 293system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 301system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 302system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id 303system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id 304system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id 306system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id 307system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses 308system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses | 298system.cpu.l2cache.tags.replacements 0 # number of replacements 299system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use 300system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 303system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 304system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 312system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id 315system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id 316system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id 317system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id 318system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses 319system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses |
| 320system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
|
| 309system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits 310system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits 311system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits 312system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits 313system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits 314system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits 315system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits 316system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 443system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 444system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 445system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 446system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 447system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 448system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 321system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits 322system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits 323system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits 324system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits 325system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits 326system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits 327system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits 328system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 455system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 461system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
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| 449system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution 451system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 473system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram 475system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) 476system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 477system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 478system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 462system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 486system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram 488system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) 489system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 490system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 491system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 494system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states |
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| 481system.membus.trans_dist::ReadResp 3160 # Transaction distribution 482system.membus.trans_dist::ReadExReq 1575 # Transaction distribution 483system.membus.trans_dist::ReadExResp 1575 # Transaction distribution 484system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution 485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) 486system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) 487system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) 488system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 495system.membus.trans_dist::ReadResp 3160 # Transaction distribution 496system.membus.trans_dist::ReadExReq 1575 # Transaction distribution 497system.membus.trans_dist::ReadExResp 1575 # Transaction distribution 498system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution 499system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) 500system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) 501system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) 502system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- |