Cross Reference: /gem5/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt

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stats.txt (11456:c0fb4435b80f)	stats.txt (11502:e273e86a873d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250987 # Number of seconds simulated 4sim_ticks 250987138500 # Number of ticks simulated 5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 637690 # Simulator instruction rate (inst/s) 8host_op_rate 1068827 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1211861746 # Simulator tick rate (ticks/s) 10host_mem_usage 298388 # Number of bytes of host memory used 11host_seconds 207.11 # Real time elapsed on the host 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 34system.cpu.workload.num_syscalls 400 # Number of system calls 35system.cpu.numCycles 501974277 # number of cpu cycles simulated 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 132071193 # Number of instructions committed 39system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 42system.cpu.num_func_calls 1595632 # number of times a function call or return occured 43system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls 44system.cpu.num_int_insts 219019986 # number of integer instructions 45system.cpu.num_fp_insts 2162459 # number of float instructions 46system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read 47system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written 48system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read 49system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written 50system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read 51system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written 52system.cpu.num_mem_refs 77165304 # number of memory refs 53system.cpu.num_load_insts 56649587 # Number of load instructions 54system.cpu.num_store_insts 20515717 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 12326938 # Number of branches fetched 60system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction 61system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction 62system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction 63system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction 64system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction 68system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction 69system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction 70system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction 71system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction 72system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction 73system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction 74system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction 75system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction 76system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction 77system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction 78system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction 79system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction 80system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction 81system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction 82system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction 83system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction 84system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction 85system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction 86system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction 87system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 90system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 91system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 221363385 # Class of executed instruction 95system.cpu.dcache.tags.replacements 41 # number of replacements 96system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use 97system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor 102system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id 110system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id 111system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses 112system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses 113system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits 114system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits 115system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits 116system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits 117system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits 118system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits 119system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits 120system.cpu.dcache.overall_hits::total 77195831 # number of overall hits 121system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses 122system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses 123system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses 124system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses 125system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses 126system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses 127system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses 128system.cpu.dcache.overall_misses::total 1905 # number of overall misses 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles 130system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles 133system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles 134system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles 135system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles 136system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles 137system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) 138system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) 139system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 140system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 141system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses 142system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses 143system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses 144system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses 145system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses 146system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 147system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses 148system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses 149system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 150system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 151system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 152system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses 153system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency 154system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency 155system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency 156system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency 157system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency 158system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency 159system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency 160system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency 161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167system.cpu.dcache.writebacks::writebacks 7 # number of writebacks 168system.cpu.dcache.writebacks::total 7 # number of writebacks 169system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses 170system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses 171system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses 172system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses 173system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses 174system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses 175system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses 176system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses 177system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles 178system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles 179system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles 180system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles 181system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles 182system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles 183system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles 184system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles 185system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses 186system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 187system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses 188system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses 189system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 190system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 191system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 192system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses 193system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency 194system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency 195system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency 196system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency 197system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 198system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 199system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 200system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 201system.cpu.icache.tags.replacements 2836 # number of replacements 202system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy 210system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 212system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 216system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id 217system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses 218system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses 219system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits 220system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits 221system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits 222system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits 223system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 224system.cpu.icache.overall_hits::total 173489673 # number of overall hits 225system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 226system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses 227system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses 228system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses 229system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses 230system.cpu.icache.overall_misses::total 4694 # number of overall misses 231system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles 232system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles 233system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles 234system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles 235system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles 236system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles 237system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) 238system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) 239system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses 240system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses 241system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses 242system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses 243system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 244system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses 245system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses 246system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 247system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses 248system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 249system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency 250system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency 251system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency 252system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency 253system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency 254system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency 255system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 260system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 261system.cpu.icache.writebacks::writebacks 2836 # number of writebacks 262system.cpu.icache.writebacks::total 2836 # number of writebacks 263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 264system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 265system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 266system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 267system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 268system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses 269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles 270system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles 271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles 272system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles 273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles 274system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles 275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses 276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses 277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 278system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 287system.cpu.l2cache.tags.replacements 0 # number of replacements 288system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use 289system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 290system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 291system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 292system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 293system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor 296system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy 300system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 302system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id 303system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id 304system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id 306system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id 307system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses 308system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses 309system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits 310system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits 311system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits 312system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits 313system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits 314system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits 315system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits 316system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits 317system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits 318system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits 319system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits 320system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits 321system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits 322system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits 323system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits 324system.cpu.l2cache.overall_hits::total 1864 # number of overall hits 325system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses 326system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses 327system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses 328system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses 329system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses 330system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses 331system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses 332system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses 333system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses 334system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses 335system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses 336system.cpu.l2cache.overall_misses::total 4735 # number of overall misses 337system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles 338system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles 339system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles 340system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles 341system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles 342system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles 343system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles 344system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles 345system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles 346system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles 347system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles 348system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles 349system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) 350system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) 351system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) 352system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) 353system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) 356system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) 357system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) 358system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 364system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses 365system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses 366system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses 367system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses 368system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses 369system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses 370system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses 371system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses 373system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses 374system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses 376system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses 377system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency 378system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency 379system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency 380system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency 381system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency 382system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency 383system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency 384system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency 385system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency 389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses 396system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses 397system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses 398system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses 399system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses 400system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses 401system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses 407system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles 408system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles 409system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles 410system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles 411system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles 412system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles 419system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses 420system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses 421system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses 422system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses 423system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses 424system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses 425system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses 426system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses 427system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses 428system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses 429system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses 430system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses 431system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency 432system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency 433system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency 434system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency 435system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency 436system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 443system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 444system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 445system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 446system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 447system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 448system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 449system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution 451system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution 457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) 459system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) 460system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) 461system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) 462system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.snoops 0 # Total snoops (count) 464system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram 469system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram 470system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 472system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram 475system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) 476system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 477system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 478system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 481system.membus.trans_dist::ReadResp 3160 # Transaction distribution 482system.membus.trans_dist::ReadExReq 1575 # Transaction distribution 483system.membus.trans_dist::ReadExResp 1575 # Transaction distribution 484system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution 485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) 486system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) 487system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) 488system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) 489system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) 490system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) 491system.membus.snoops 0 # Total snoops (count) 492system.membus.snoop_fanout::samples 4735 # Request fanout histogram 493system.membus.snoop_fanout::mean 0 # Request fanout histogram 494system.membus.snoop_fanout::stdev 0 # Request fanout histogram 495system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 496system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram 497system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 498system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 499system.membus.snoop_fanout::min_value 0 # Request fanout histogram 500system.membus.snoop_fanout::max_value 0 # Request fanout histogram 501system.membus.snoop_fanout::total 4735 # Request fanout histogram 502system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks) 503system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 504system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks) 505system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 506 507---------- End Simulation Statistics ----------

stats.txt (11456:c0fb4435b80f)

stats.txt (11502:e273e86a873d)

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.250987 # Number of seconds simulated
4sim_ticks 250987138500 # Number of ticks simulated
5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 637690 # Simulator instruction rate (inst/s)
8host_op_rate 1068827 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1211861746 # Simulator tick rate (ticks/s)
10host_mem_usage 298388 # Number of bytes of host memory used
11host_seconds 207.11 # Real time elapsed on the host
12sim_insts 132071193 # Number of instructions simulated
13sim_ops 221363385 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
34system.cpu.workload.num_syscalls 400 # Number of system calls
35system.cpu.numCycles 501974277 # number of cpu cycles simulated
36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
38system.cpu.committedInsts 132071193 # Number of instructions committed
39system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
40system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
41system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
42system.cpu.num_func_calls 1595632 # number of times a function call or return occured
43system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
44system.cpu.num_int_insts 219019986 # number of integer instructions
45system.cpu.num_fp_insts 2162459 # number of float instructions
46system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
47system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
48system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
49system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
50system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
51system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
52system.cpu.num_mem_refs 77165304 # number of memory refs
53system.cpu.num_load_insts 56649587 # Number of load instructions
54system.cpu.num_store_insts 20515717 # Number of store instructions
55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
56system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
59system.cpu.Branches 12326938 # Number of branches fetched
60system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
61system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
62system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
63system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
64system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
65system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
66system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
67system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
68system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
69system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
70system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
71system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
72system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
73system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
74system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
75system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
76system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
77system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
78system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
79system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
80system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
81system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
82system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
83system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
84system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
85system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
86system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
87system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
89system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
90system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
91system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
94system.cpu.op_class::total 221363385 # Class of executed instruction
95system.cpu.dcache.tags.replacements 41 # number of replacements
96system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
97system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
98system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
99system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
101system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
102system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
103system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
104system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
105system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
106system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
107system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
108system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id
109system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
110system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
111system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
112system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
113system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
114system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
115system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
116system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
117system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
118system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
119system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
120system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
121system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
122system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
123system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
124system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
125system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
126system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
127system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
128system.cpu.dcache.overall_misses::total 1905 # number of overall misses
129system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
130system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
131system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
132system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
133system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
134system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
135system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
136system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
137system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
138system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
139system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
140system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
141system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
142system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
143system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
144system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
145system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
146system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
147system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
148system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
149system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
150system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
151system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
152system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
153system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
154system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
155system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
156system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
157system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
158system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
159system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
160system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
167system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
168system.cpu.dcache.writebacks::total 7 # number of writebacks
169system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
170system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
171system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
172system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
173system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
174system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
175system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
176system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
177system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles
178system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles
179system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles
180system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles
181system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles
182system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles
183system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles
184system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
185system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
186system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
187system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
188system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
189system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
190system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
191system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
192system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
193system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency
194system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency
195system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency
196system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency
197system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
198system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
199system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
200system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
201system.cpu.icache.tags.replacements 2836 # number of replacements
202system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
203system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
204system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
205system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
207system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor
208system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy
209system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy
210system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
211system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
212system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
213system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
214system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id
215system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
216system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
217system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
218system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
219system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
220system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
221system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
222system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
223system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
224system.cpu.icache.overall_hits::total 173489673 # number of overall hits
225system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
226system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
227system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
228system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
229system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
230system.cpu.icache.overall_misses::total 4694 # number of overall misses
231system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles
232system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles
233system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles
234system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles
235system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles
236system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
237system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
238system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
239system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
240system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
241system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
242system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
243system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
244system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
245system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
246system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
247system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
248system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
249system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency
250system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency
251system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
252system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency
253system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
254system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency
255system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
256system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
257system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
258system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
259system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
260system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
261system.cpu.icache.writebacks::writebacks 2836 # number of writebacks
262system.cpu.icache.writebacks::total 2836 # number of writebacks
263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
264system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
265system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
266system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
267system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
268system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles
270system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles
271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles
272system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles
273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles
274system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles
275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
278system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
280system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency
282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency
283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
284system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
286system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
287system.cpu.l2cache.tags.replacements 0 # number of replacements
288system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
289system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
290system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
291system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks.
292system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
293system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor
294system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor
295system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor
296system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
297system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy
298system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
299system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy
300system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
301system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
302system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
303system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
304system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
305system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
306system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
307system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
308system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
309system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits
310system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits
311system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits
312system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits
313system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
314system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
315system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits
316system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits
317system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits
318system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits
319system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
320system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
321system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
322system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
323system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
324system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
325system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
326system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
327system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses
328system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses
329system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses
330system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses
331system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
332system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
333system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
334system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
335system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
336system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
337system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles
338system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles
339system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles
340system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles
341system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles
342system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles
343system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles
344system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles
345system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles
346system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles
347system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles
348system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles
349system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses)
350system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses)
351system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses)
352system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses)
353system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
354system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
355system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses)
356system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses)
357system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses)
358system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses)
359system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
360system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
361system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
362system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
363system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
364system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
365system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
366system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
367system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses
368system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses
369system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses
370system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses
371system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
372system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
373system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
374system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
375system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
376system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
377system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency
378system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency
379system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency
380system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency
381system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency
382system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency
383system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
384system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
385system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency
386system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
388system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency
389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
395system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
396system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
397system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses
398system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses
399system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses
400system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses
401system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
402system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
403system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
404system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
405system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
406system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
407system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles
408system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles
409system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles
410system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles
411system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles
412system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles
413system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles
414system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles
415system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles
416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles
417system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles
418system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles
419system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
420system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
421system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses
422system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses
423system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses
424system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses
425system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
426system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
427system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
428system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
429system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
430system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
431system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
432system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
433system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
434system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
435system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
436system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
439system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
443system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
444system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
445system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
446system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
447system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
448system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
449system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
450system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
451system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
452system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
453system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
454system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
455system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution
456system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution
457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes)
458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes)
459system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes)
460system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes)
461system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
462system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes)
463system.cpu.toL2Bus.snoops 0 # Total snoops (count)
464system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram
465system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram
466system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram
467system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
468system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram
469system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram
470system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram
475system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks)
476system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
477system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
478system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
479system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
480system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
481system.membus.trans_dist::ReadResp 3160 # Transaction distribution
482system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
483system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
484system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution
485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
486system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
487system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
488system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
489system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
490system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
491system.membus.snoops 0 # Total snoops (count)
492system.membus.snoop_fanout::samples 4735 # Request fanout histogram
493system.membus.snoop_fanout::mean 0 # Request fanout histogram
494system.membus.snoop_fanout::stdev 0 # Request fanout histogram
495system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
496system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
497system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
498system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
499system.membus.snoop_fanout::min_value 0 # Request fanout histogram
500system.membus.snoop_fanout::max_value 0 # Request fanout histogram
501system.membus.snoop_fanout::total 4735 # Request fanout histogram
502system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks)
503system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
504system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks)
505system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
506
507---------- End Simulation Statistics ----------