| stats.txt (11312:3d7a85d71bd1) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250987 # Number of seconds simulated 4sim_ticks 250987138500 # Number of ticks simulated 5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250987 # Number of seconds simulated 4sim_ticks 250987138500 # Number of ticks simulated 5final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 290260 # Simulator instruction rate (inst/s) 8host_op_rate 486501 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 551606975 # Simulator tick rate (ticks/s) 10host_mem_usage 279340 # Number of bytes of host memory used 11host_seconds 455.01 # Real time elapsed on the host | 7host_inst_rate 637690 # Simulator instruction rate (inst/s) 8host_op_rate 1068827 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1211861746 # Simulator tick rate (ticks/s) 10host_mem_usage 298388 # Number of bytes of host memory used 11host_seconds 207.11 # Real time elapsed on the host |
| 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory --- 139 unchanged lines hidden (view full) --- 159system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency 160system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency 161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory --- 139 unchanged lines hidden (view full) --- 159system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency 160system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency 161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 167system.cpu.dcache.fast_writes 0 # number of fast writes performed 168system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 169system.cpu.dcache.writebacks::writebacks 7 # number of writebacks 170system.cpu.dcache.writebacks::total 7 # number of writebacks 171system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses 172system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses 173system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses 175system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses 176system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses --- 18 unchanged lines hidden (view full) --- 195system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency 196system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency 197system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency 199system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 201system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency | 167system.cpu.dcache.writebacks::writebacks 7 # number of writebacks 168system.cpu.dcache.writebacks::total 7 # number of writebacks 169system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses 170system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses 171system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses 172system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses 173system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses 174system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses --- 18 unchanged lines hidden (view full) --- 193system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency 194system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency 195system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency 196system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency 197system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 198system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency 199system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency 200system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency |
| 203system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 204system.cpu.icache.tags.replacements 2836 # number of replacements 205system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use 206system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 207system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 208system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 209system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 210system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor 211system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 256system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency 257system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency 258system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 259system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 261system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 262system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 263system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 201system.cpu.icache.tags.replacements 2836 # number of replacements 202system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 253system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency 254system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency 255system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 260system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 264system.cpu.icache.fast_writes 0 # number of fast writes performed 265system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 266system.cpu.icache.writebacks::writebacks 2836 # number of writebacks 267system.cpu.icache.writebacks::total 2836 # number of writebacks 268system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 269system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 270system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 271system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 272system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 273system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 284system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 285system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 286system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency 287system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency 288system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 289system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 290system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 291system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency | 261system.cpu.icache.writebacks::writebacks 2836 # number of writebacks 262system.cpu.icache.writebacks::total 2836 # number of writebacks 263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 264system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 265system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 266system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 267system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 268system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency |
| 292system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 293system.cpu.l2cache.tags.replacements 0 # number of replacements 294system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use 295system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 296system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 297system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 298system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 299system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor 300system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 393system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency 394system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency 395system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 287system.cpu.l2cache.tags.replacements 0 # number of replacements 288system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use 289system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 290system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 291system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 292system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 293system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency 389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 401system.cpu.l2cache.fast_writes 0 # number of fast writes performed 402system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 403system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses 404system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses 405system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses 406system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses 407system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses 408system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses 409system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses 410system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 443system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency | 395system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses 396system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses 397system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses 398system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses 399system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses 400system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses 401system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 435system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency 436system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency |
| 451system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 452system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution --- 57 unchanged lines hidden --- | 443system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 444system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 445system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 446system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 447system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 448system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 449system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution --- 57 unchanged lines hidden --- |