| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250954 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250954 # Number of seconds simulated |
| 4sim_ticks 250953957500 # Number of ticks simulated 5final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 250953958500 # Number of ticks simulated 5final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 750520 # Simulator instruction rate (inst/s) 8host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1426094126 # Simulator tick rate (ticks/s) 10host_mem_usage 340216 # Number of bytes of host memory used 11host_seconds 175.97 # Real time elapsed on the host | 7host_inst_rate 759533 # Simulator instruction rate (inst/s) 8host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1443220819 # Simulator tick rate (ticks/s) 10host_mem_usage 343748 # Number of bytes of host memory used 11host_seconds 173.88 # Real time elapsed on the host |
| 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory --- 7 unchanged lines hidden (view full) --- 27system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 34system.cpu.workload.num_syscalls 400 # Number of system calls | 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory --- 7 unchanged lines hidden (view full) --- 27system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 34system.cpu.workload.num_syscalls 400 # Number of system calls |
| 35system.cpu.numCycles 501907915 # number of cpu cycles simulated | 35system.cpu.numCycles 501907917 # number of cpu cycles simulated |
| 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 132071193 # Number of instructions committed 39system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 42system.cpu.num_func_calls 1595632 # number of times a function call or return occured 43system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 48system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read 49system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written 50system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read 51system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written 52system.cpu.num_mem_refs 77165304 # number of memory refs 53system.cpu.num_load_insts 56649587 # Number of load instructions 54system.cpu.num_store_insts 20515717 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 132071193 # Number of instructions committed 39system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 42system.cpu.num_func_calls 1595632 # number of times a function call or return occured 43system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 48system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read 49system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written 50system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read 51system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written 52system.cpu.num_mem_refs 77165304 # number of memory refs 53system.cpu.num_load_insts 56649587 # Number of load instructions 54system.cpu.num_store_insts 20515717 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 56system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles | 56system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles |
| 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 12326938 # Number of branches fetched 60system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction 61system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction 62system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction 63system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction 64system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 90system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 91system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 221363385 # Class of executed instruction 95system.cpu.dcache.tags.replacements 41 # number of replacements | 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 12326938 # Number of branches fetched 60system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction 61system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction 62system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction 63system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction 64system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 90system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 91system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 221363385 # Class of executed instruction 95system.cpu.dcache.tags.replacements 41 # number of replacements |
| 96system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use | 96system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use |
| 97system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 97system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 101system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor | 101system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor |
| 102system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id --- 87 unchanged lines hidden (view full) --- 197system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency 199system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency 201system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency 203system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 204system.cpu.icache.tags.replacements 2836 # number of replacements | 102system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id --- 87 unchanged lines hidden (view full) --- 197system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency 199system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency 201system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency 203system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 204system.cpu.icache.tags.replacements 2836 # number of replacements |
| 205system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use | 205system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use |
| 206system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 207system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 208system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 209system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 206system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 207system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 208system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 209system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 210system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor | 210system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor |
| 211system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy 212system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id 217system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id 218system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 226system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 227system.cpu.icache.overall_hits::total 173489673 # number of overall hits 228system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 229system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses 230system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses 231system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses 232system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses 233system.cpu.icache.overall_misses::total 4694 # number of overall misses | 211system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy 212system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id 217system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id 218system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 226system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 227system.cpu.icache.overall_hits::total 173489673 # number of overall hits 228system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 229system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses 230system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses 231system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses 232system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses 233system.cpu.icache.overall_misses::total 4694 # number of overall misses |
| 234system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles 235system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles 236system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles 237system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles 238system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles 239system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles | 234system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles 235system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles 236system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles 237system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles 238system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles 239system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles |
| 240system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) 241system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) 242system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses 243system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses 244system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses 245system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses 246system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 247system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses 248system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses 249system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 250system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses 251system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses | 240system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) 241system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) 242system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses 243system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses 244system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses 245system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses 246system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 247system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses 248system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses 249system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 250system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses 251system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses |
| 252system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency 253system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency 254system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency 255system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency 256system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency 257system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency | 252system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency 253system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency 254system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency 255system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency 256system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency 257system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency |
| 258system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 259system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 261system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 262system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 263system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 264system.cpu.icache.fast_writes 0 # number of fast writes performed 265system.cpu.icache.cache_copies 0 # number of cache copies performed 266system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 267system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 268system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 269system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 270system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 271system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses | 258system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 259system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 261system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 262system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 263system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 264system.cpu.icache.fast_writes 0 # number of fast writes performed 265system.cpu.icache.cache_copies 0 # number of cache copies performed 266system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 267system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 268system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 269system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 270system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 271system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses |
| 272system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles 273system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles 274system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles 275system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles 276system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles 277system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles | 272system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles 273system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles 274system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles 275system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles 276system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles 277system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles |
| 278system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses 279system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses 280system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 281system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 282system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 283system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 278system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses 279system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses 280system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 281system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 282system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 283system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 284system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency 285system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency 286system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency 287system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency 288system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency 289system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency | 284system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency 285system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency 286system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency 287system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency 288system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency 289system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency |
| 290system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 291system.cpu.l2cache.tags.replacements 0 # number of replacements | 290system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 291system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 292system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use | 292system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use |
| 293system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 294system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 295system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 296system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 297system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor | 293system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. 294system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 295system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. 296system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 297system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor |
| 298system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor | 298system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor |
| 299system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor 300system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy 301system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy 302system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy 303system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy 304system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 306system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id --- 131 unchanged lines hidden (view full) --- 438system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency 440system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency 441system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency 443system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency 444system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency 445system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 299system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor 300system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy 301system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy 302system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy 303system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy 304system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 306system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id --- 131 unchanged lines hidden (view full) --- 438system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency 440system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency 441system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency 443system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency 444system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency 445system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 446system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. 447system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. 448system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 449system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 450system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 451system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 446system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 447system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution 448system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution 449system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 451system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution 453system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) 454system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) 455system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) 456system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) 457system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) 459system.cpu.toL2Bus.snoops 0 # Total snoops (count) 460system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram | 452system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 457system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution 458system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution 459system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) 460system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) 461system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) 462system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) 465system.cpu.toL2Bus.snoops 0 # Total snoops (count) 466system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram |
| 461system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 467system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram |
| 463system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 469system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 464system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram | 470system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram |
| 466system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 472system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 468system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 474system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 469system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 470system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram 471system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) 472system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 473system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 474system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 475system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 476system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 27 unchanged lines hidden --- | 475system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 476system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram 477system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) 478system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 481system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 482system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 27 unchanged lines hidden --- |