3,5c3,5
< sim_seconds 0.250987 # Number of seconds simulated
< sim_ticks 250987138500 # Number of ticks simulated
< final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.250992 # Number of seconds simulated
> sim_ticks 250991873500 # Number of ticks simulated
> final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 493662 # Simulator instruction rate (inst/s)
< host_op_rate 827423 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 938152393 # Simulator tick rate (ticks/s)
< host_mem_usage 294200 # Number of bytes of host memory used
< host_seconds 267.53 # Real time elapsed on the host
---
> host_inst_rate 1054537 # Simulator instruction rate (inst/s)
> host_op_rate 1767501 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2004072574 # Simulator tick rate (ticks/s)
> host_mem_usage 299608 # Number of bytes of host memory used
> host_seconds 125.24 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
37,38c37,38
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
40,41c40,41
< system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 501974277 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 501983747 # number of cpu cycles simulated
62c62
< system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles
101c101
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
103c103
< system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use
108,110c108,110
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy
120c120
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
137,144c137,144
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles
161,168c161,168
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency
185,192c185,192
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles
201,209c201,209
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
211c211
< system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use
216,218c216,218
< system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy
222,223c222,223
< system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id
228c228
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
241,246c241,246
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles
259,264c259,264
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency
279,284c279,284
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles
291,297c291,297
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
299,302c299,302
< system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks.
304,307c304,305
< system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor
309,320c307,318
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
349,360c347,358
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles
389,400c387,398
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency
419,430c417,428
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles
443,454c441,452
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency
461c459
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
495c493,499
< system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.250987 # Number of seconds simulated
< sim_ticks 250987138500 # Number of ticks simulated
< final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.250992 # Number of seconds simulated
> sim_ticks 250991873500 # Number of ticks simulated
> final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 493662 # Simulator instruction rate (inst/s)
< host_op_rate 827423 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 938152393 # Simulator tick rate (ticks/s)
< host_mem_usage 294200 # Number of bytes of host memory used
< host_seconds 267.53 # Real time elapsed on the host
---
> host_inst_rate 1054537 # Simulator instruction rate (inst/s)
> host_op_rate 1767501 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2004072574 # Simulator tick rate (ticks/s)
> host_mem_usage 299608 # Number of bytes of host memory used
> host_seconds 125.24 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
37,38c37,38
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
40,41c40,41
< system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 501974277 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 501983747 # number of cpu cycles simulated
62c62
< system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles
101c101
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
103c103
< system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use
108,110c108,110
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy
120c120
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
137,144c137,144
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles
161,168c161,168
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency
185,192c185,192
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles
201,209c201,209
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
211c211
< system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use
216,218c216,218
< system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy
222,223c222,223
< system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id
228c228
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
241,246c241,246
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles
259,264c259,264
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency
279,284c279,284
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles
291,297c291,297
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
299,302c299,302
< system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks.
304,307c304,305
< system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor
309,320c307,318
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
349,360c347,358
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles
389,400c387,398
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency
419,430c417,428
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles
443,454c441,452
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency
461c459
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states
495c493,499
< system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states