4,5c4,5
< sim_ticks 250953957500 # Number of ticks simulated
< final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 250953958500 # Number of ticks simulated
> final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 750520 # Simulator instruction rate (inst/s)
< host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1426094126 # Simulator tick rate (ticks/s)
< host_mem_usage 340216 # Number of bytes of host memory used
< host_seconds 175.97 # Real time elapsed on the host
---
> host_inst_rate 759533 # Simulator instruction rate (inst/s)
> host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1443220819 # Simulator tick rate (ticks/s)
> host_mem_usage 343748 # Number of bytes of host memory used
> host_seconds 173.88 # Real time elapsed on the host
35c35
< system.cpu.numCycles 501907915 # number of cpu cycles simulated
---
> system.cpu.numCycles 501907917 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles
96c96
< system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use
101c101
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor
205c205
< system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use
210c210
< system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor
234,239c234,239
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles
252,257c252,257
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency
272,277c272,277
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles
284,289c284,289
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency
292c292
< system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use
298c298
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor
445a446,451
> system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
461,462c467,468
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram
464,465c470,471
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram
468c474
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 250953957500 # Number of ticks simulated
< final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 250953958500 # Number of ticks simulated
> final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 750520 # Simulator instruction rate (inst/s)
< host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1426094126 # Simulator tick rate (ticks/s)
< host_mem_usage 340216 # Number of bytes of host memory used
< host_seconds 175.97 # Real time elapsed on the host
---
> host_inst_rate 759533 # Simulator instruction rate (inst/s)
> host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1443220819 # Simulator tick rate (ticks/s)
> host_mem_usage 343748 # Number of bytes of host memory used
> host_seconds 173.88 # Real time elapsed on the host
35c35
< system.cpu.numCycles 501907915 # number of cpu cycles simulated
---
> system.cpu.numCycles 501907917 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles
96c96
< system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use
101c101
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor
205c205
< system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use
210c210
< system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor
234,239c234,239
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles
252,257c252,257
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency
272,277c272,277
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles
284,289c284,289
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency
292c292
< system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use
298c298
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor
445a446,451
> system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
461,462c467,468
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram
464,465c470,471
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram
468c474
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram