1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
17default_p_state=UNDEFINED |
18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 55 56[system.cpu] 57type=TimingSimpleCPU 58children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 |
63default_p_state=UNDEFINED |
64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 |
79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null |
83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload --- 8 unchanged lines hidden (view full) --- 99 100[system.cpu.dcache] 101type=Cache 102children=tags 103addr_ranges=0:18446744073709551615 104assoc=2 105clk_domain=system.cpu_clk_domain 106clusivity=mostly_incl |
107default_p_state=UNDEFINED |
108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false 112max_miss_count=0 113mshrs=4 |
114p_state_clk_gate_bins=20 115p_state_clk_gate_max=1000000000000 116p_state_clk_gate_min=1000 117power_model=Null |
118prefetch_on_access=false 119prefetcher=Null 120response_latency=2 121sequential_access=false 122size=262144 123system=system 124tags=system.cpu.dcache.tags 125tgts_per_mshr=20 126write_buffers=8 127writeback_clean=false 128cpu_side=system.cpu.dcache_port 129mem_side=system.cpu.toL2Bus.slave[1] 130 131[system.cpu.dcache.tags] 132type=LRU 133assoc=2 134block_size=64 135clk_domain=system.cpu_clk_domain |
136default_p_state=UNDEFINED |
137eventq_index=0 138hit_latency=2 |
139p_state_clk_gate_bins=20 140p_state_clk_gate_max=1000000000000 141p_state_clk_gate_min=1000 142power_model=Null |
143sequential_access=false 144size=262144 145 146[system.cpu.dtb] 147type=X86TLB 148children=walker 149eventq_index=0 150size=64 151walker=system.cpu.dtb.walker 152 153[system.cpu.dtb.walker] 154type=X86PagetableWalker 155clk_domain=system.cpu_clk_domain |
156default_p_state=UNDEFINED |
157eventq_index=0 158num_squash_per_cycle=4 |
159p_state_clk_gate_bins=20 160p_state_clk_gate_max=1000000000000 161p_state_clk_gate_min=1000 162power_model=Null |
163system=system 164port=system.cpu.toL2Bus.slave[3] 165 166[system.cpu.icache] 167type=Cache 168children=tags 169addr_ranges=0:18446744073709551615 170assoc=2 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl |
173default_p_state=UNDEFINED |
174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true 178max_miss_count=0 179mshrs=4 |
180p_state_clk_gate_bins=20 181p_state_clk_gate_max=1000000000000 182p_state_clk_gate_min=1000 183power_model=Null |
184prefetch_on_access=false 185prefetcher=Null 186response_latency=2 187sequential_access=false 188size=131072 189system=system 190tags=system.cpu.icache.tags 191tgts_per_mshr=20 192write_buffers=8 193writeback_clean=true 194cpu_side=system.cpu.icache_port 195mem_side=system.cpu.toL2Bus.slave[0] 196 197[system.cpu.icache.tags] 198type=LRU 199assoc=2 200block_size=64 201clk_domain=system.cpu_clk_domain |
202default_p_state=UNDEFINED |
203eventq_index=0 204hit_latency=2 |
205p_state_clk_gate_bins=20 206p_state_clk_gate_max=1000000000000 207p_state_clk_gate_min=1000 208power_model=Null |
209sequential_access=false 210size=131072 211 212[system.cpu.interrupts] 213type=X86LocalApic 214clk_domain=system.cpu.apic_clk_domain |
215default_p_state=UNDEFINED |
216eventq_index=0 217int_latency=1000 |
218p_state_clk_gate_bins=20 219p_state_clk_gate_max=1000000000000 220p_state_clk_gate_min=1000 |
221pio_addr=2305843009213693952 222pio_latency=100000 |
223power_model=Null |
224system=system 225int_master=system.membus.slave[2] 226int_slave=system.membus.master[2] 227pio=system.membus.master[1] 228 229[system.cpu.isa] 230type=X86ISA 231eventq_index=0 232 233[system.cpu.itb] 234type=X86TLB 235children=walker 236eventq_index=0 237size=64 238walker=system.cpu.itb.walker 239 240[system.cpu.itb.walker] 241type=X86PagetableWalker 242clk_domain=system.cpu_clk_domain |
243default_p_state=UNDEFINED |
244eventq_index=0 245num_squash_per_cycle=4 |
246p_state_clk_gate_bins=20 247p_state_clk_gate_max=1000000000000 248p_state_clk_gate_min=1000 249power_model=Null |
250system=system 251port=system.cpu.toL2Bus.slave[2] 252 253[system.cpu.l2cache] 254type=Cache 255children=tags 256addr_ranges=0:18446744073709551615 257assoc=8 258clk_domain=system.cpu_clk_domain 259clusivity=mostly_incl |
260default_p_state=UNDEFINED |
261demand_mshr_reserve=1 262eventq_index=0 263hit_latency=20 264is_read_only=false 265max_miss_count=0 266mshrs=20 |
267p_state_clk_gate_bins=20 268p_state_clk_gate_max=1000000000000 269p_state_clk_gate_min=1000 270power_model=Null |
271prefetch_on_access=false 272prefetcher=Null 273response_latency=20 274sequential_access=false 275size=2097152 276system=system 277tags=system.cpu.l2cache.tags 278tgts_per_mshr=12 279write_buffers=8 280writeback_clean=false 281cpu_side=system.cpu.toL2Bus.master[0] 282mem_side=system.membus.slave[1] 283 284[system.cpu.l2cache.tags] 285type=LRU 286assoc=8 287block_size=64 288clk_domain=system.cpu_clk_domain |
289default_p_state=UNDEFINED |
290eventq_index=0 291hit_latency=20 |
292p_state_clk_gate_bins=20 293p_state_clk_gate_max=1000000000000 294p_state_clk_gate_min=1000 295power_model=Null |
296sequential_access=false 297size=2097152 298 299[system.cpu.toL2Bus] 300type=CoherentXBar 301children=snoop_filter 302clk_domain=system.cpu_clk_domain |
303default_p_state=UNDEFINED |
304eventq_index=0 305forward_latency=0 306frontend_latency=1 |
307p_state_clk_gate_bins=20 308p_state_clk_gate_max=1000000000000 309p_state_clk_gate_min=1000 |
310point_of_coherency=false |
311power_model=Null |
312response_latency=1 313snoop_filter=system.cpu.toL2Bus.snoop_filter 314snoop_response_latency=1 315system=system 316use_default_range=false 317width=32 318master=system.cpu.l2cache.cpu_side 319slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port --- 14 unchanged lines hidden (view full) --- 334cmd=twolf smred 335cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing 336drivers= 337egid=100 338env= 339errout=cerr 340euid=100 341eventq_index=0 |
342executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf |
343gid=100 344input=cin 345kvmInSE=false 346max_stack_size=67108864 347output=cout 348pid=100 349ppid=99 350simpoint=0 --- 15 unchanged lines hidden (view full) --- 366enable=false 367eventq_index=0 368sys_clk_domain=system.clk_domain 369transition_latency=100000000 370 371[system.membus] 372type=CoherentXBar 373clk_domain=system.clk_domain |
374default_p_state=UNDEFINED |
375eventq_index=0 376forward_latency=4 377frontend_latency=3 |
378p_state_clk_gate_bins=20 379p_state_clk_gate_max=1000000000000 380p_state_clk_gate_min=1000 |
381point_of_coherency=true |
382power_model=Null |
383response_latency=2 384snoop_filter=Null 385snoop_response_latency=4 386system=system 387use_default_range=false 388width=16 389master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 390slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 391 392[system.physmem] 393type=SimpleMemory 394bandwidth=73.000000 395clk_domain=system.clk_domain 396conf_table_reported=true |
397default_p_state=UNDEFINED |
398eventq_index=0 399in_addr_map=true 400latency=30000 401latency_var=0 402null=false |
403p_state_clk_gate_bins=20 404p_state_clk_gate_max=1000000000000 405p_state_clk_gate_min=1000 406power_model=Null |
407range=0:134217727 408port=system.membus.master[0] 409 410[system.voltage_domain] 411type=VoltageDomain 412eventq_index=0 413voltage=1.000000 414 |