| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.270600 # Number of seconds simulated 4sim_ticks 270599529500 # Number of ticks simulated 5final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.270605 # Number of seconds simulated 4sim_ticks 270604702500 # Number of ticks simulated 5final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1216795 # Simulator instruction rate (inst/s) 8host_op_rate 1216796 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1702111428 # Simulator tick rate (ticks/s) 10host_mem_usage 252676 # Number of bytes of host memory used 11host_seconds 158.98 # Real time elapsed on the host | 7host_inst_rate 1707855 # Simulator instruction rate (inst/s) 8host_op_rate 1707857 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2389075229 # Simulator tick rate (ticks/s) 10host_mem_usage 256284 # Number of bytes of host memory used 11host_seconds 113.27 # Real time elapsed on the host |
| 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 19system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 19system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 25system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 401 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 401 # Number of system calls |
| 36system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 541199059 # number of cpu cycles simulated | 36system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 541209405 # number of cpu cycles simulated |
| 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 193444518 # Number of instructions committed 41system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 44system.cpu.num_func_calls 1957920 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 46system.cpu.num_int_insts 167974806 # number of integer instructions 47system.cpu.num_fp_insts 1970372 # number of float instructions 48system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 49system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 52system.cpu.num_mem_refs 76733958 # number of memory refs 53system.cpu.num_load_insts 57735091 # Number of load instructions 54system.cpu.num_store_insts 18998867 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 193444518 # Number of instructions committed 41system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 44system.cpu.num_func_calls 1957920 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 46system.cpu.num_int_insts 167974806 # number of integer instructions 47system.cpu.num_fp_insts 1970372 # number of float instructions 48system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 49system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 52system.cpu.num_mem_refs 76733958 # number of memory refs 53system.cpu.num_load_insts 57735091 # Number of load instructions 54system.cpu.num_store_insts 18998867 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 56system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles | 56system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles |
| 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 15132745 # Number of branches fetched 60system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 61system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 64system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 90system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 91system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 193445773 # Class of executed instruction | 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 15132745 # Number of branches fetched 60system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 61system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 64system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 90system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 91system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 193445773 # Class of executed instruction |
| 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 96system.cpu.dcache.tags.replacements 2 # number of replacements | 96system.cpu.dcache.tags.replacements 2 # number of replacements |
| 97system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use | 97system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use |
| 98system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 98system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 102system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy | 102system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy |
| 105system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 111system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 112system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 113system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses | 105system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 111system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 112system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 113system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses |
| 114system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 114system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 115system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits --- 4 unchanged lines hidden (view full) --- 127system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 128system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 129system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 130system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 131system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 134system.cpu.dcache.overall_misses::total 1575 # number of overall misses | 115system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits --- 4 unchanged lines hidden (view full) --- 127system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 128system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 129system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 130system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 131system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 134system.cpu.dcache.overall_misses::total 1575 # number of overall misses |
| 135system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles 139system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles 140system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles 141system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles | 135system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles 139system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles 140system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles 141system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles |
| 145system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 150system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 151system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 152system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 157system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 158system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 159system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 160system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses | 145system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 150system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 151system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 152system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 157system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 158system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 159system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 160system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses |
| 165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency 167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency 170system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency 171system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 172system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency | 165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency 167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency 170system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency 171system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency 172system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency |
| 175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 182system.cpu.dcache.writebacks::total 2 # number of writebacks 183system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 184system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 186system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 187system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 188system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 189system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 190system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 191system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 192system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses | 175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 182system.cpu.dcache.writebacks::total 2 # number of writebacks 183system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 184system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 186system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 187system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 188system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 189system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 190system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 191system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 192system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses |
| 193system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles 195system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles 196system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles 197system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles 198system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles 199system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles | 193system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles 195system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles 196system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles 197system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles 198system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles 199system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles |
| 203system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 204system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 208system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 209system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 210system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 211system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 212system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses | 203system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 204system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 208system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 209system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 210system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 211system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 212system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses |
| 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency 214system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 218system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 220system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 222system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 223system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency 214system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency 216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency 218system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency 220system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency 222system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency 223system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 224system.cpu.icache.tags.replacements 10362 # number of replacements | 224system.cpu.icache.tags.replacements 10362 # number of replacements |
| 225system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use | 225system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use |
| 226system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 227system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 228system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 229system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 226system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 227system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 228system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 229system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 230system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 231system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy | 230system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor 231system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy |
| 233system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 239system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 240system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 241system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses | 233system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 239system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 240system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 241system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses |
| 242system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 242system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 243system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 244system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 245system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 246system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 247system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 248system.cpu.icache.overall_hits::total 193433248 # number of overall hits 249system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 250system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 251system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 252system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 253system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 254system.cpu.icache.overall_misses::total 12288 # number of overall misses | 243system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 244system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 245system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 246system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 247system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 248system.cpu.icache.overall_hits::total 193433248 # number of overall hits 249system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 250system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 251system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 252system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 253system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 254system.cpu.icache.overall_misses::total 12288 # number of overall misses |
| 255system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles 256system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles 257system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles 258system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles 259system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles 260system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles | 255system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles 256system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles 257system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles 258system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles 259system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles 260system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles |
| 261system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 262system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 264system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 265system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 266system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 267system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 269system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 270system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 271system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 272system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses | 261system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 262system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 264system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 265system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 266system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 267system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 269system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 270system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 271system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 272system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses |
| 273system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency 274system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency 275system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 276system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency 277system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency | 273system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency 274system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency 275system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency 276system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency 277system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency |
| 279system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.icache.writebacks::writebacks 10362 # number of writebacks 286system.cpu.icache.writebacks::total 10362 # number of writebacks 287system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 288system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 289system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 290system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 291system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 292system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses | 279system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.icache.writebacks::writebacks 10362 # number of writebacks 286system.cpu.icache.writebacks::total 10362 # number of writebacks 287system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 288system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 289system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 290system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 291system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 292system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses |
| 293system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles 294system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles 295system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles 298system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles | 293system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles 294system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles 295system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles 298system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles |
| 299system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 301system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 302system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 304system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses | 299system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 301system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 302system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 304system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses |
| 305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 308system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 311system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency 306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency 307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency 308system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency 311system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 312system.cpu.l2cache.tags.replacements 0 # number of replacements | 312system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 313system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 314system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 315system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 316system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. | 313system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use 314system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks. 315system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks. 316system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks. |
| 317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 318system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor 320system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor 321system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 322system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 324system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id | 318system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor 320system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy 322system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id |
| 326system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id | 324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id |
| 327system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 329system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 330system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 331system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 332system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 333system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses 334system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id 329system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id 330system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses 331system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses 332system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 335system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 336system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 337system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 338system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 339system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 340system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 341system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 342system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits --- 6 unchanged lines hidden (view full) --- 349system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 350system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 351system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 352system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 353system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 354system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 355system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 356system.cpu.l2cache.overall_misses::total 5173 # number of overall misses | 333system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 334system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 335system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 336system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 337system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 338system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 339system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 340system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits --- 6 unchanged lines hidden (view full) --- 347system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 348system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 349system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 350system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 351system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 352system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 353system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 354system.cpu.l2cache.overall_misses::total 5173 # number of overall misses |
| 357system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles 358system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles 359system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles 360system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles 361system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles 362system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles 363system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles 364system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles 365system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles 366system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles 367system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles 368system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles | 355system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles 356system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles 357system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles 358system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles 359system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles 360system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles 361system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles 362system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles 363system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles 364system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles 365system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles 366system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles |
| 369system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) 370system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) 371system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) 372system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) 373system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 374system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 375system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 376system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 389system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 390system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 391system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 392system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 393system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 394system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 395system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 396system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses | 367system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) 368system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) 369system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) 370system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) 371system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 372system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 373system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 374system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 387system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 388system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 389system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 390system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 391system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 392system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 393system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 394system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses |
| 397system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency 398system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency 399system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency 400system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency 401system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency 402system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency 403system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 404system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 405system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency 406system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 407system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 408system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency | 395system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency 396system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency 397system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency 398system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency 399system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency 400system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency 401system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency 402system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency 403system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency 404system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency 405system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency 406system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency |
| 409system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 416system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 417system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 418system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 419system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 420system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 421system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 422system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 423system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 424system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 425system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 426system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses | 407system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 408system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 409system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 410system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 411system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 412system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 413system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 414system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 415system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 416system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 417system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 418system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 419system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 420system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 421system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 422system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 423system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 424system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses |
| 427system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles 428system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles 429system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles 430system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles 431system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles 432system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles 433system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles 434system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles 435system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles 436system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles 437system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles 438system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles | 425system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles 426system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles 427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles 428system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles 429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles 430system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles 431system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles 432system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles 433system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles 434system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles 435system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles 436system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles |
| 439system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 440system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 441system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 442system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 443system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 444system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 445system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 446system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 447system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 448system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 449system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 450system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses | 437system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 438system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 439system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 440system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 442system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 443system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 444system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 445system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 446system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 447system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 448system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses |
| 451system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency 452system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency 453system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency 454system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency 455system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency 456system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency 457system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 458system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 459system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 462system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency | 449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency 450system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency 451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency 452system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency 453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency 454system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency 455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency 456system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency 457system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency 458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency 459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency 460system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency |
| 463system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 464system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 465system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 466system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 467system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 468system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 461system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 464system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 469system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 467system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 470system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 477system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) --- 16 unchanged lines hidden (view full) --- 494system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 496system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 497system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 498system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 499system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 500system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 501system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 468system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 475system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) --- 16 unchanged lines hidden (view full) --- 492system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 494system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 495system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 496system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 497system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 498system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 499system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 502system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states | 500system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. 501system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 502system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 503system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 504system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 505system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 506system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states |
| 503system.membus.trans_dist::ReadResp 4095 # Transaction distribution 504system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 505system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 506system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 507system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 508system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 509system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 510system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- | 507system.membus.trans_dist::ReadResp 4095 # Transaction distribution 508system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 509system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 510system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 511system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 512system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 513system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 514system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- |