| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270600 # Number of seconds simulated 4sim_ticks 270599529500 # Number of ticks simulated 5final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270600 # Number of seconds simulated 4sim_ticks 270599529500 # Number of ticks simulated 5final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 833752 # Simulator instruction rate (inst/s) 8host_op_rate 833752 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1166291607 # Simulator tick rate (ticks/s) 10host_mem_usage 251752 # Number of bytes of host memory used 11host_seconds 232.02 # Real time elapsed on the host | 7host_inst_rate 1741327 # Simulator instruction rate (inst/s) 8host_op_rate 1741329 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2435851420 # Simulator tick rate (ticks/s) 10host_mem_usage 298736 # Number of bytes of host memory used 11host_seconds 111.09 # Real time elapsed on the host |
| 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 19system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 401 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 401 # Number of system calls |
| 36system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states |
|
| 34system.cpu.numCycles 541199059 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 193444518 # Number of instructions committed 38system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 41system.cpu.num_func_calls 1957920 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 84system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 88system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 193445773 # Class of executed instruction | 37system.cpu.numCycles 541199059 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 193444518 # Number of instructions committed 41system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 44system.cpu.num_func_calls 1957920 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 90system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 91system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 193445773 # Class of executed instruction |
| 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 92system.cpu.dcache.tags.replacements 2 # number of replacements 93system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 107system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 108system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 109system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses | 96system.cpu.dcache.tags.replacements 2 # number of replacements 97system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use 98system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 102system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy 105system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 111system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 112system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 113system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses |
| 114system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 110system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 111system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 112system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 113system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 114system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 115system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 116system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 117system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 214system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 215system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 216system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency | 115system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 218system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 220system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 222system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency |
| 223system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 218system.cpu.icache.tags.replacements 10362 # number of replacements 219system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 220system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 221system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 222system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 223system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 225system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy 226system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy 227system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 229system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 233system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 234system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 235system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses | 224system.cpu.icache.tags.replacements 10362 # number of replacements 225system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 226system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 227system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 228system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 229system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 230system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 231system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy 233system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 239system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 240system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 241system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses |
| 242system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 236system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 237system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 238system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 239system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 240system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 241system.cpu.icache.overall_hits::total 193433248 # number of overall hits 242system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 243system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 296system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 297system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 298system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 300system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 302system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency | 243system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 244system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 245system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 246system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 247system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 248system.cpu.icache.overall_hits::total 193433248 # number of overall hits 249system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 250system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 304system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 308system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency |
| 311system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 304system.cpu.l2cache.tags.replacements 0 # number of replacements 305system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 306system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 307system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 308system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 309system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 310system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 311system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 318system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 324system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 325system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses | 312system.cpu.l2cache.tags.replacements 0 # number of replacements 313system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 314system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 315system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 316system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 318system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 326system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 329system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 330system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 331system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 332system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 333system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses |
| 334system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
|
| 326system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 327system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 328system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 329system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 330system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 331system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 332system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 333system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits --- 118 unchanged lines hidden (view full) --- 452system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 454system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 455system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 456system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 457system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 458system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 459system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 335system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 336system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 337system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 338system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 339system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 340system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 341system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 342system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits --- 118 unchanged lines hidden (view full) --- 461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 462system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 463system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 464system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 465system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 466system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 467system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 468system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 469system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
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| 460system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 467system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 483system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 485system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 486system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 487system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 488system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 489system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 490system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 470system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 477system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 493system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 495system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 496system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 497system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 498system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 499system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 500system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 501system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states |
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| 491system.membus.trans_dist::ReadResp 4095 # Transaction distribution 492system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 493system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 494system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 495system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 496system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 497system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 498system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 502system.membus.trans_dist::ReadResp 4095 # Transaction distribution 503system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 504system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 505system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 506system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 507system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 508system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 509system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |