| stats.txt (11312:3d7a85d71bd1) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270600 # Number of seconds simulated 4sim_ticks 270599529500 # Number of ticks simulated 5final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270600 # Number of seconds simulated 4sim_ticks 270599529500 # Number of ticks simulated 5final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 568132 # Simulator instruction rate (inst/s) 8host_op_rate 568133 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 794730164 # Simulator tick rate (ticks/s) 10host_mem_usage 235264 # Number of bytes of host memory used 11host_seconds 340.49 # Real time elapsed on the host | 7host_inst_rate 1248385 # Simulator instruction rate (inst/s) 8host_op_rate 1248386 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1746300725 # Simulator tick rate (ticks/s) 10host_mem_usage 255364 # Number of bytes of host memory used 11host_seconds 154.96 # Real time elapsed on the host |
| 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory --- 148 unchanged lines hidden (view full) --- 168system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 169system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency 170system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory --- 148 unchanged lines hidden (view full) --- 168system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 169system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency 170system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 176system.cpu.dcache.fast_writes 0 # number of fast writes performed 177system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 178system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 179system.cpu.dcache.writebacks::total 2 # number of writebacks 180system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 181system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 182system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 183system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 184system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 185system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 212system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 213system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 215system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency | 176system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 177system.cpu.dcache.writebacks::total 2 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 182system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 183system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 214system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 215system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 216system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency |
| 220system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 221system.cpu.icache.tags.replacements 10362 # number of replacements 222system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 223system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 228system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 273system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 274system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency 275system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 280system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 218system.cpu.icache.tags.replacements 10362 # number of replacements 219system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 220system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 221system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 222system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 223system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 225system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 270system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency 272system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 276system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 277system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 281system.cpu.icache.fast_writes 0 # number of fast writes performed 282system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 283system.cpu.icache.writebacks::writebacks 10362 # number of writebacks 284system.cpu.icache.writebacks::total 10362 # number of writebacks 285system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 286system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 287system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 288system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 289system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 290system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 301system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 302system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 304system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 306system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 308system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency | 278system.cpu.icache.writebacks::writebacks 10362 # number of writebacks 279system.cpu.icache.writebacks::total 10362 # number of writebacks 280system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 281system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 282system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 283system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 284system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 285system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 296system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 297system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 298system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 300system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 302system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency |
| 309system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 310system.cpu.l2cache.tags.replacements 0 # number of replacements 311system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 312system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 313system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 314system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 315system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 316system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor --- 86 unchanged lines hidden (view full) --- 404system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 405system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency 406system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 304system.cpu.l2cache.tags.replacements 0 # number of replacements 305system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 306system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 307system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 308system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 309system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 310system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 311system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor --- 86 unchanged lines hidden (view full) --- 398system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 399system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency 400system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 401system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 402system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 403system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 404system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 405system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 412system.cpu.l2cache.fast_writes 0 # number of fast writes performed 413system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 414system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 415system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 416system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 417system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 418system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 419system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 420system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 421system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 454system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency 455system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency 456system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 457system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 458system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 461system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency | 406system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 407system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 408system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 409system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 410system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 411system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 412system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 413system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 446system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency 447system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency 448system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 449system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 451system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 452system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency |
| 462system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 463system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 464system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 465system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 466system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 467system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 468system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 469system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution --- 54 unchanged lines hidden --- | 454system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 455system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 456system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 457system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 458system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 459system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 460system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution --- 54 unchanged lines hidden --- |