| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270563 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270563 # Number of seconds simulated |
| 4sim_ticks 270563082500 # Number of ticks simulated 5final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 270563083500 # Number of ticks simulated 5final_tick 270563083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1293394 # Simulator instruction rate (inst/s) 8host_op_rate 1293395 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1809017316 # Simulator tick rate (ticks/s) 10host_mem_usage 297764 # Number of bytes of host memory used 11host_seconds 149.56 # Real time elapsed on the host | 7host_inst_rate 1207450 # Simulator instruction rate (inst/s) 8host_op_rate 1207451 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1688810940 # Simulator tick rate (ticks/s) 10host_mem_usage 300136 # Number of bytes of host memory used 11host_seconds 160.21 # Real time elapsed on the host |
| 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory --- 6 unchanged lines hidden (view full) --- 26system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 401 # Number of system calls | 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory --- 6 unchanged lines hidden (view full) --- 26system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 401 # Number of system calls |
| 34system.cpu.numCycles 541126165 # number of cpu cycles simulated | 34system.cpu.numCycles 541126167 # number of cpu cycles simulated |
| 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 193444518 # Number of instructions committed 38system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 41system.cpu.num_func_calls 1957920 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 43system.cpu.num_int_insts 167974806 # number of integer instructions 44system.cpu.num_fp_insts 1970372 # number of float instructions 45system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 46system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 49system.cpu.num_mem_refs 76733958 # number of memory refs 50system.cpu.num_load_insts 57735091 # Number of load instructions 51system.cpu.num_store_insts 18998867 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 193444518 # Number of instructions committed 38system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 41system.cpu.num_func_calls 1957920 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 43system.cpu.num_int_insts 167974806 # number of integer instructions 44system.cpu.num_fp_insts 1970372 # number of float instructions 45system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 46system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 49system.cpu.num_mem_refs 76733958 # number of memory refs 50system.cpu.num_load_insts 57735091 # Number of load instructions 51system.cpu.num_store_insts 18998867 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 53system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles | 53system.cpu.num_busy_cycles 541126166.998000 # Number of busy cycles |
| 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 15132745 # Number of branches fetched 57system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 58system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 61system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 88system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 193445773 # Class of executed instruction 92system.cpu.dcache.tags.replacements 2 # number of replacements | 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 15132745 # Number of branches fetched 57system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 58system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 61system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 88system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 193445773 # Class of executed instruction 92system.cpu.dcache.tags.replacements 2 # number of replacements |
| 93system.cpu.dcache.tags.tagsinuse 1237.203933 # Cycle average of tags in use | 93system.cpu.dcache.tags.tagsinuse 1237.203935 # Cycle average of tags in use |
| 94system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 94system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 98system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203933 # Average occupied blocks per requestor | 98system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203935 # Average occupied blocks per requestor |
| 99system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id --- 107 unchanged lines hidden (view full) --- 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency 215system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 220system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 221system.cpu.icache.tags.replacements 10362 # number of replacements | 99system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id --- 107 unchanged lines hidden (view full) --- 214system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency 215system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 220system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 221system.cpu.icache.tags.replacements 10362 # number of replacements |
| 222system.cpu.icache.tags.tagsinuse 1591.579161 # Cycle average of tags in use | 222system.cpu.icache.tags.tagsinuse 1591.579162 # Cycle average of tags in use |
| 223system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 223system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 227system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579161 # Average occupied blocks per requestor | 227system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579162 # Average occupied blocks per requestor |
| 228system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 243system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 244system.cpu.icache.overall_hits::total 193433248 # number of overall hits 245system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 246system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 247system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 248system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 249system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 250system.cpu.icache.overall_misses::total 12288 # number of overall misses | 228system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 243system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 244system.cpu.icache.overall_hits::total 193433248 # number of overall hits 245system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 246system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 247system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 248system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 249system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 250system.cpu.icache.overall_misses::total 12288 # number of overall misses |
| 251system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles 252system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles 253system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles 254system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles 255system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles 256system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles | 251system.cpu.icache.ReadReq_miss_latency::cpu.inst 310819500 # number of ReadReq miss cycles 252system.cpu.icache.ReadReq_miss_latency::total 310819500 # number of ReadReq miss cycles 253system.cpu.icache.demand_miss_latency::cpu.inst 310819500 # number of demand (read+write) miss cycles 254system.cpu.icache.demand_miss_latency::total 310819500 # number of demand (read+write) miss cycles 255system.cpu.icache.overall_miss_latency::cpu.inst 310819500 # number of overall miss cycles 256system.cpu.icache.overall_miss_latency::total 310819500 # number of overall miss cycles |
| 257system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 258system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 260system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 261system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 262system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 263system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 264system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 265system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 266system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 267system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 268system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses | 257system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 258system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 260system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 261system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 262system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 263system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 264system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 265system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 266system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 267system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 268system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses |
| 269system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency 270system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency 271system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency 272system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency 273system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency 274system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency | 269system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.555664 # average ReadReq miss latency 270system.cpu.icache.ReadReq_avg_miss_latency::total 25294.555664 # average ReadReq miss latency 271system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency 272system.cpu.icache.demand_avg_miss_latency::total 25294.555664 # average overall miss latency 273system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency 274system.cpu.icache.overall_avg_miss_latency::total 25294.555664 # average overall miss latency |
| 275system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 280system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 281system.cpu.icache.fast_writes 0 # number of fast writes performed 282system.cpu.icache.cache_copies 0 # number of cache copies performed 283system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 284system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 285system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 286system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 287system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 288system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses | 275system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 280system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 281system.cpu.icache.fast_writes 0 # number of fast writes performed 282system.cpu.icache.cache_copies 0 # number of cache copies performed 283system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 284system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 285system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 286system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 287system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 288system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses |
| 289system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298530500 # number of ReadReq MSHR miss cycles 290system.cpu.icache.ReadReq_mshr_miss_latency::total 298530500 # number of ReadReq MSHR miss cycles 291system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298530500 # number of demand (read+write) MSHR miss cycles 292system.cpu.icache.demand_mshr_miss_latency::total 298530500 # number of demand (read+write) MSHR miss cycles 293system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298530500 # number of overall MSHR miss cycles 294system.cpu.icache.overall_mshr_miss_latency::total 298530500 # number of overall MSHR miss cycles | 289system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298531500 # number of ReadReq MSHR miss cycles 290system.cpu.icache.ReadReq_mshr_miss_latency::total 298531500 # number of ReadReq MSHR miss cycles 291system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298531500 # number of demand (read+write) MSHR miss cycles 292system.cpu.icache.demand_mshr_miss_latency::total 298531500 # number of demand (read+write) MSHR miss cycles 293system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298531500 # number of overall MSHR miss cycles 294system.cpu.icache.overall_mshr_miss_latency::total 298531500 # number of overall MSHR miss cycles |
| 295system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 296system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 297system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 298system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 299system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 300system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses | 295system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 296system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 297system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 298system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 299system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 300system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses |
| 301system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.474284 # average ReadReq mshr miss latency 302system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.474284 # average ReadReq mshr miss latency 303system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency 304system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency 305system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency 306system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency | 301system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.555664 # average ReadReq mshr miss latency 302system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.555664 # average ReadReq mshr miss latency 303system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency 304system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency 305system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency 306system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency |
| 307system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 308system.cpu.l2cache.tags.replacements 0 # number of replacements | 307system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 308system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 309system.cpu.l2cache.tags.tagsinuse 2678.340822 # Cycle average of tags in use | 309system.cpu.l2cache.tags.tagsinuse 2678.340828 # Cycle average of tags in use |
| 310system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 311system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 312system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 313system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 314system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor | 310system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 311system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 312system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 313system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 314system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor |
| 315system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282887 # Average occupied blocks per requestor | 315system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282891 # Average occupied blocks per requestor |
| 316system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 320system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 323system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id --- 125 unchanged lines hidden (view full) --- 449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 452system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 455system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency 456system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 316system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 320system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 323system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id --- 125 unchanged lines hidden (view full) --- 449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 452system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 455system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency 456system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 457system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 458system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 459system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 460system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 461system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 462system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 457system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 458system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 464system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 465system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.snoops 0 # Total snoops (count) 471system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram | 463system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 470system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 475system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.snoops 0 # Total snoops (count) 477system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram |
| 472system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 478system.cpu.toL2Bus.snoop_fanout::mean 0.000041 # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::stdev 0.006425 # Request fanout histogram |
| 474system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 480system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 475system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 476system.cpu.toL2Bus.snoop_fanout::1 24228 100.00% 100.00% # Request fanout histogram | 481system.cpu.toL2Bus.snoop_fanout::0 24227 100.00% 100.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram |
| 477system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 483system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 479system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 485system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 480system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram 482system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) 483system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 484system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 485system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 486system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 487system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 25 unchanged lines hidden --- | 486system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram 488system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) 489system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 490system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 491system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 25 unchanged lines hidden --- |