3,5c3,5
< sim_seconds 0.270600 # Number of seconds simulated
< sim_ticks 270599529500 # Number of ticks simulated
< final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.270605 # Number of seconds simulated
> sim_ticks 270604702500 # Number of ticks simulated
> final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1216795 # Simulator instruction rate (inst/s)
< host_op_rate 1216796 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1702111428 # Simulator tick rate (ticks/s)
< host_mem_usage 252676 # Number of bytes of host memory used
< host_seconds 158.98 # Real time elapsed on the host
---
> host_inst_rate 1707855 # Simulator instruction rate (inst/s)
> host_op_rate 1707857 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2389075229 # Simulator tick rate (ticks/s)
> host_mem_usage 256284 # Number of bytes of host memory used
> host_seconds 113.27 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 541199059 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 541209405 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use
102,104c102,104
< system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy
114c114
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
135,144c135,144
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles
165,174c165,174
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency
193,202c193,202
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles
213,223c213,223
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
225c225
< system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use
230,232c230,232
< system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy
242c242
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
255,260c255,260
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles
273,278c273,278
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency
293,298c293,298
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles
305,311c305,311
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
313,316c313,316
< system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks.
318,325c318,323
< system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id
327,334c325,332
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
357,368c355,366
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles
397,408c395,406
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency
427,438c425,436
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles
451,462c449,460
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency
469c467
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
502c500,506
< system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.270600 # Number of seconds simulated
< sim_ticks 270599529500 # Number of ticks simulated
< final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.270605 # Number of seconds simulated
> sim_ticks 270604702500 # Number of ticks simulated
> final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1216795 # Simulator instruction rate (inst/s)
< host_op_rate 1216796 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1702111428 # Simulator tick rate (ticks/s)
< host_mem_usage 252676 # Number of bytes of host memory used
< host_seconds 158.98 # Real time elapsed on the host
---
> host_inst_rate 1707855 # Simulator instruction rate (inst/s)
> host_op_rate 1707857 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2389075229 # Simulator tick rate (ticks/s)
> host_mem_usage 256284 # Number of bytes of host memory used
> host_seconds 113.27 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 541199059 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 541209405 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use
102,104c102,104
< system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy
114c114
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
135,144c135,144
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles
< system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles
> system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles
165,174c165,174
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency
< system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency
> system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency
193,202c193,202
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles
213,223c213,223
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency
< system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency
> system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
225c225
< system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use
230,232c230,232
< system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy
242c242
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
255,260c255,260
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles
273,278c273,278
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency
293,298c293,298
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles
305,311c305,311
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
313,316c313,316
< system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks.
318,325c318,323
< system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id
327,334c325,332
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
357,368c355,366
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles
397,408c395,406
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency
427,438c425,436
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles
451,462c449,460
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency
469c467
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states
502c500,506
< system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states