| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.099596 # Number of seconds simulated 4sim_ticks 99596491500 # Number of ticks simulated 5final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.099596 # Number of seconds simulated 4sim_ticks 99596491500 # Number of ticks simulated 5final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 2176341 # Simulator instruction rate (inst/s) 8host_op_rate 2294214 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1257887009 # Simulator tick rate (ticks/s) 10host_mem_usage 304976 # Number of bytes of host memory used 11host_seconds 79.18 # Real time elapsed on the host | 7host_inst_rate 2111044 # Simulator instruction rate (inst/s) 8host_op_rate 2225381 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1220146763 # Simulator tick rate (ticks/s) 10host_mem_usage 306656 # Number of bytes of host memory used 11host_seconds 81.63 # Real time elapsed on the host |
| 12sim_insts 172317410 # Number of instructions simulated 13sim_ops 181650342 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172317410 # Number of instructions simulated 13sim_ops 181650342 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory 18system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory 22system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory --- 6 unchanged lines hidden (view full) --- 30system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory 19system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory 23system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory --- 6 unchanged lines hidden (view full) --- 31system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) |
| 39system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 38system.cpu_clk_domain.clock 500 # Clock period in ticks | 40system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 39system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 60system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 68system.cpu.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 89system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.dtb.read_accesses 0 # DTB read accesses 92system.cpu.dtb.write_accesses 0 # DTB write accesses 93system.cpu.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.dtb.hits 0 # DTB hits 95system.cpu.dtb.misses 0 # DTB misses 96system.cpu.dtb.accesses 0 # DTB accesses | 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses |
| 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 97system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 118system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 400 # Number of system calls | 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses 161system.cpu.workload.num_syscalls 400 # Number of system calls |
| 162system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states |
|
| 156system.cpu.numCycles 199192984 # number of cpu cycles simulated 157system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 158system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 159system.cpu.committedInsts 172317410 # Number of instructions committed 160system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed 161system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 162system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses 163system.cpu.num_func_calls 3545028 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 208system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction 209system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction 210system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction 211system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction 212system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction 213system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 214system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::total 181650743 # Class of executed instruction | 163system.cpu.numCycles 199192984 # number of cpu cycles simulated 164system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.committedInsts 172317410 # Number of instructions committed 167system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed 168system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 169system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses 170system.cpu.num_func_calls 3545028 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 215system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction 216system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction 217system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction 218system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction 219system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction 220system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 221system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 222system.cpu.op_class::total 181650743 # Class of executed instruction |
| 223system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states |
|
| 216system.membus.trans_dist::ReadReq 217614903 # Transaction distribution 217system.membus.trans_dist::ReadResp 217637310 # Transaction distribution 218system.membus.trans_dist::WriteReq 12364287 # Transaction distribution 219system.membus.trans_dist::WriteResp 12364287 # Transaction distribution 220system.membus.trans_dist::SoftPFReq 463 # Transaction distribution 221system.membus.trans_dist::SoftPFResp 463 # Transaction distribution 222system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution 223system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution --- 20 unchanged lines hidden --- | 224system.membus.trans_dist::ReadReq 217614903 # Transaction distribution 225system.membus.trans_dist::ReadResp 217637310 # Transaction distribution 226system.membus.trans_dist::WriteReq 12364287 # Transaction distribution 227system.membus.trans_dist::WriteResp 12364287 # Transaction distribution 228system.membus.trans_dist::SoftPFReq 463 # Transaction distribution 229system.membus.trans_dist::SoftPFResp 463 # Transaction distribution 230system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution 231system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution --- 20 unchanged lines hidden --- |