| 1Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
2Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
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1gem5 Simulator System. http://gem5.org
2gem5 is copyrighted software; use the --copyright option for details.
3
| 3gem5 Simulator System. http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
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4gem5 compiled Jun 17 2015 08:02:53
5gem5 started Jun 17 2015 09:01:31
6gem5 executing on e104799-lin
7command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /work/gem5/outgoing/gem5_2/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
| 6gem5 compiled Nov 15 2015 14:58:33
7gem5 started Nov 15 2015 14:58:46
8gem5 executing on ribera.cs.wisc.edu, pid 5048
9command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /scratch/nilay/GEM5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
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8
9Global frequency set at 1000000000000 ticks per second
10info: Entering event queue @ 0. Starting simulation...
11Exiting @ tick 100000000000 because simulate() limit reached
| 10
11Global frequency set at 1000000000000 ticks per second
12info: Entering event queue @ 0. Starting simulation...
13Exiting @ tick 100000000000 because simulate() limit reached
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