| 1Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout 2Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
|
1gem5 Simulator System. http://gem5.org 2gem5 is copyrighted software; use the --copyright option for details. 3
| 3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5
|
4gem5 compiled Aug 25 2012 13:56:00 5gem5 started Aug 25 2012 13:58:17 6gem5 executing on Andreas-MacBook-Pro.local 7command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem
| 6gem5 compiled Sep 22 2013 05:53:51 7gem5 started Sep 22 2013 05:53:54 8gem5 executing on zizzer 9command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
|
8Global frequency set at 1000000000000 ticks per second 9info: Entering event queue @ 0. Starting simulation... 10Exiting @ tick 100000000000 because simulate() limit reached
| 10Global frequency set at 1000000000000 ticks per second 11info: Entering event queue @ 0. Starting simulation... 12Exiting @ tick 100000000000 because simulate() limit reached
|