| stats.txt (11530:6e143fd2cabf) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000014 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000014 # Number of seconds simulated |
| 4sim_ticks 14181 # Number of ticks simulated 5final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 13821 # Number of ticks simulated 5final_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000 # Frequency of simulated ticks | 6sim_freq 1000000000 # Frequency of simulated ticks |
| 7host_tick_rate 238683 # Simulator tick rate (ticks/s) 8host_mem_usage 530468 # Number of bytes of host memory used | 7host_tick_rate 213268 # Simulator tick rate (ticks/s) 8host_mem_usage 483832 # Number of bytes of host memory used |
| 9host_seconds 0.06 # Real time elapsed on the host 10system.voltage_domain.voltage 1 # Voltage in Volts 11system.clk_domain.clock 1 # Clock period in ticks | 9host_seconds 0.06 # Real time elapsed on the host 10system.voltage_domain.voltage 1 # Voltage in Volts 11system.clk_domain.clock 1 # Clock period in ticks |
| 12system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 13system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory 14system.mem_ctrls.bytes_read::total 16576 # Number of bytes read from this memory 15system.mem_ctrls.bytes_written::dir_cntrl0 576 # Number of bytes written to this memory 16system.mem_ctrls.bytes_written::total 576 # Number of bytes written to this memory 17system.mem_ctrls.num_reads::dir_cntrl0 259 # Number of read requests responded to by this memory 18system.mem_ctrls.num_reads::total 259 # Number of read requests responded to by this memory 19system.mem_ctrls.num_writes::dir_cntrl0 9 # Number of write requests responded to by this memory 20system.mem_ctrls.num_writes::total 9 # Number of write requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 1168887949 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 1168887949 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_write::dir_cntrl0 40617728 # Write bandwidth from this memory (bytes/s) 24system.mem_ctrls.bw_write::total 40617728 # Write bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_total::dir_cntrl0 1209505677 # Total bandwidth to/from this memory (bytes/s) 26system.mem_ctrls.bw_total::total 1209505677 # Total bandwidth to/from this memory (bytes/s) 27system.mem_ctrls.readReqs 259 # Number of read requests accepted 28system.mem_ctrls.writeReqs 9 # Number of write requests accepted 29system.mem_ctrls.readBursts 259 # Number of DRAM read bursts, including those serviced by the write queue 30system.mem_ctrls.writeBursts 9 # Number of DRAM write bursts, including those merged in the write queue 31system.mem_ctrls.bytesReadDRAM 15936 # Total number of bytes read from DRAM 32system.mem_ctrls.bytesReadWrQ 640 # Total number of bytes read from write queue | 12system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 13system.mem_ctrls.bytes_read::dir_cntrl0 16384 # Number of bytes read from this memory 14system.mem_ctrls.bytes_read::total 16384 # Number of bytes read from this memory 15system.mem_ctrls.bytes_written::dir_cntrl0 896 # Number of bytes written to this memory 16system.mem_ctrls.bytes_written::total 896 # Number of bytes written to this memory 17system.mem_ctrls.num_reads::dir_cntrl0 256 # Number of read requests responded to by this memory 18system.mem_ctrls.num_reads::total 256 # Number of read requests responded to by this memory 19system.mem_ctrls.num_writes::dir_cntrl0 14 # Number of write requests responded to by this memory 20system.mem_ctrls.num_writes::total 14 # Number of write requests responded to by this memory 21system.mem_ctrls.bw_read::dir_cntrl0 1185442443 # Total read bandwidth from this memory (bytes/s) 22system.mem_ctrls.bw_read::total 1185442443 # Total read bandwidth from this memory (bytes/s) 23system.mem_ctrls.bw_write::dir_cntrl0 64828884 # Write bandwidth from this memory (bytes/s) 24system.mem_ctrls.bw_write::total 64828884 # Write bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_total::dir_cntrl0 1250271326 # Total bandwidth to/from this memory (bytes/s) 26system.mem_ctrls.bw_total::total 1250271326 # Total bandwidth to/from this memory (bytes/s) 27system.mem_ctrls.readReqs 256 # Number of read requests accepted 28system.mem_ctrls.writeReqs 14 # Number of write requests accepted 29system.mem_ctrls.readBursts 256 # Number of DRAM read bursts, including those serviced by the write queue 30system.mem_ctrls.writeBursts 14 # Number of DRAM write bursts, including those merged in the write queue 31system.mem_ctrls.bytesReadDRAM 15488 # Total number of bytes read from DRAM 32system.mem_ctrls.bytesReadWrQ 896 # Total number of bytes read from write queue |
| 33system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM | 33system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM |
| 34system.mem_ctrls.bytesReadSys 16576 # Total read bytes from the system interface side 35system.mem_ctrls.bytesWrittenSys 576 # Total written bytes from the system interface side 36system.mem_ctrls.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue | 34system.mem_ctrls.bytesReadSys 16384 # Total read bytes from the system interface side 35system.mem_ctrls.bytesWrittenSys 896 # Total written bytes from the system interface side 36system.mem_ctrls.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue |
| 37system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 38system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 37system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 38system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 39system.mem_ctrls.perBankRdBursts::0 100 # Per bank write bursts 40system.mem_ctrls.perBankRdBursts::1 71 # Per bank write bursts 41system.mem_ctrls.perBankRdBursts::2 66 # Per bank write bursts | 39system.mem_ctrls.perBankRdBursts::0 99 # Per bank write bursts 40system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts 41system.mem_ctrls.perBankRdBursts::2 62 # Per bank write bursts |
| 42system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 65system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 71system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 72system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry | 42system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 65system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 71system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 72system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry |
| 73system.mem_ctrls.totGap 13941 # Total gap between requests | 73system.mem_ctrls.totGap 13710 # Total gap between requests |
| 74system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 75system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 76system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 77system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) | 74system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 75system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 76system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 77system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) |
| 80system.mem_ctrls.readPktSize::6 259 # Read request sizes (log2) | 80system.mem_ctrls.readPktSize::6 256 # Read request sizes (log2) |
| 81system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 82system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 83system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 84system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) | 81system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 82system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 83system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 84system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) |
| 87system.mem_ctrls.writePktSize::6 9 # Write request sizes (log2) 88system.mem_ctrls.rdQLenPdf::0 214 # What read queue length does an incoming req see 89system.mem_ctrls.rdQLenPdf::1 27 # What read queue length does an incoming req see 90system.mem_ctrls.rdQLenPdf::2 7 # What read queue length does an incoming req see | 87system.mem_ctrls.writePktSize::6 14 # Write request sizes (log2) 88system.mem_ctrls.rdQLenPdf::0 199 # What read queue length does an incoming req see 89system.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see 90system.mem_ctrls.rdQLenPdf::2 6 # What read queue length does an incoming req see |
| 91system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 22 unchanged lines hidden (view full) --- 121system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 122system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see | 91system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 22 unchanged lines hidden (view full) --- 121system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 122system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see |
| 129system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see | 129system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see |
| 134system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see --- 42 unchanged lines hidden (view full) --- 184system.mem_ctrls.bytesPerActivate::samples 15 # Bytes accessed per row activation 185system.mem_ctrls.bytesPerActivate::mean 913.066667 # Bytes accessed per row activation 186system.mem_ctrls.bytesPerActivate::gmean 883.543279 # Bytes accessed per row activation 187system.mem_ctrls.bytesPerActivate::stdev 210.139908 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation | 134system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see --- 42 unchanged lines hidden (view full) --- 184system.mem_ctrls.bytesPerActivate::samples 15 # Bytes accessed per row activation 185system.mem_ctrls.bytesPerActivate::mean 913.066667 # Bytes accessed per row activation 186system.mem_ctrls.bytesPerActivate::gmean 883.543279 # Bytes accessed per row activation 187system.mem_ctrls.bytesPerActivate::stdev 210.139908 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation |
| 192system.mem_ctrls.totQLat 973 # Total ticks spent queuing 193system.mem_ctrls.totMemAccLat 5704 # Total ticks spent from burst creation until serviced by the DRAM 194system.mem_ctrls.totBusLat 1245 # Total ticks spent in databus transfers 195system.mem_ctrls.avgQLat 3.91 # Average queueing delay per DRAM burst | 192system.mem_ctrls.totQLat 2184 # Total ticks spent queuing 193system.mem_ctrls.totMemAccLat 6782 # Total ticks spent from burst creation until serviced by the DRAM 194system.mem_ctrls.totBusLat 1210 # Total ticks spent in databus transfers 195system.mem_ctrls.avgQLat 9.02 # Average queueing delay per DRAM burst |
| 196system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst | 196system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst |
| 197system.mem_ctrls.avgMemAccLat 22.91 # Average memory access latency per DRAM burst 198system.mem_ctrls.avgRdBW 1123.76 # Average DRAM read bandwidth in MiByte/s | 197system.mem_ctrls.avgMemAccLat 28.02 # Average memory access latency per DRAM burst 198system.mem_ctrls.avgRdBW 1120.61 # Average DRAM read bandwidth in MiByte/s |
| 199system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 199system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 200system.mem_ctrls.avgRdBWSys 1168.89 # Average system read bandwidth in MiByte/s 201system.mem_ctrls.avgWrBWSys 40.62 # Average system write bandwidth in MiByte/s | 200system.mem_ctrls.avgRdBWSys 1185.44 # Average system read bandwidth in MiByte/s 201system.mem_ctrls.avgWrBWSys 64.83 # Average system write bandwidth in MiByte/s |
| 202system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 202system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 203system.mem_ctrls.busUtil 8.78 # Data bus utilization in percentage 204system.mem_ctrls.busUtilRead 8.78 # Data bus utilization in percentage for reads | 203system.mem_ctrls.busUtil 8.75 # Data bus utilization in percentage 204system.mem_ctrls.busUtilRead 8.75 # Data bus utilization in percentage for reads |
| 205system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 205system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 206system.mem_ctrls.avgRdQLen 1.17 # Average read queue length when enqueuing 207system.mem_ctrls.avgWrQLen 2.63 # Average write queue length when enqueuing 208system.mem_ctrls.readRowHits 230 # Number of row buffer hits during reads | 206system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing 207system.mem_ctrls.avgWrQLen 3.35 # Average write queue length when enqueuing 208system.mem_ctrls.readRowHits 223 # Number of row buffer hits during reads |
| 209system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes | 209system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes |
| 210system.mem_ctrls.readRowHitRate 92.37 # Row buffer hit rate for reads | 210system.mem_ctrls.readRowHitRate 92.15 # Row buffer hit rate for reads |
| 211system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes | 211system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes |
| 212system.mem_ctrls.avgGap 52.02 # Average gap between requests 213system.mem_ctrls.pageHitRate 89.15 # Row buffer hit rate, read and write combined 214system.mem_ctrls_0.actEnergy 83160 # Energy for activate commands per rank (pJ) 215system.mem_ctrls_0.preEnergy 46200 # Energy for precharge commands per rank (pJ) 216system.mem_ctrls_0.readEnergy 1872000 # Energy for read commands per rank (pJ) | 212system.mem_ctrls.avgGap 50.78 # Average gap between requests 213system.mem_ctrls.pageHitRate 87.11 # Row buffer hit rate, read and write combined 214system.mem_ctrls_0.actEnergy 135660 # Energy for activate commands per rank (pJ) 215system.mem_ctrls_0.preEnergy 57960 # Energy for precharge commands per rank (pJ) 216system.mem_ctrls_0.readEnergy 2764608 # Energy for read commands per rank (pJ) |
| 217system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 217system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 218system.mem_ctrls_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) 219system.mem_ctrls_0.actBackEnergy 5437116 # Energy for active background per rank (pJ) 220system.mem_ctrls_0.preBackEnergy 58200 # Energy for precharge background per rank (pJ) 221system.mem_ctrls_0.totalEnergy 8005236 # Total energy per rank (pJ) 222system.mem_ctrls_0.averagePower 994.933632 # Core power per rank (mW) 223system.mem_ctrls_0.memoryStateTime::IDLE 83 # Time in different power states | 218system.mem_ctrls_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 219system.mem_ctrls_0.actBackEnergy 2757888 # Energy for active background per rank (pJ) 220system.mem_ctrls_0.preBackEnergy 44928 # Energy for precharge background per rank (pJ) 221system.mem_ctrls_0.actPowerDownEnergy 3490680 # Energy for active power-down per rank (pJ) 222system.mem_ctrls_0.prePowerDownEnergy 384 # Energy for precharge power-down per rank (pJ) 223system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 224system.mem_ctrls_0.totalEnergy 9866748 # Total energy per rank (pJ) 225system.mem_ctrls_0.averagePower 713.895377 # Core power per rank (mW) 226system.mem_ctrls_0.totalIdleTime 7568 # Total Idle time Per DRAM Rank 227system.mem_ctrls_0.memoryStateTime::IDLE 89 # Time in different power states |
| 224system.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states | 228system.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states |
| 225system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 226system.mem_ctrls_0.memoryStateTime::ACT 7717 # Time in different power states 227system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 229system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states 230system.mem_ctrls_0.memoryStateTime::PRE_PDN 1 # Time in different power states 231system.mem_ctrls_0.memoryStateTime::ACT 5816 # Time in different power states 232system.mem_ctrls_0.memoryStateTime::ACT_PDN 7655 # Time in different power states |
| 228system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) 229system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) 230system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) 231system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 233system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) 234system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) 235system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) 236system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 232system.mem_ctrls_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) 233system.mem_ctrls_1.actBackEnergy 168264 # Energy for active background per rank (pJ) 234system.mem_ctrls_1.preBackEnergy 4671600 # Energy for precharge background per rank (pJ) 235system.mem_ctrls_1.totalEnergy 5348424 # Total energy per rank (pJ) 236system.mem_ctrls_1.averagePower 665.889442 # Core power per rank (mW) | 237system.mem_ctrls_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 238system.mem_ctrls_1.actBackEnergy 112176 # Energy for active background per rank (pJ) 239system.mem_ctrls_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) 240system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) 241system.mem_ctrls_1.prePowerDownEnergy 2217600 # Energy for precharge power-down per rank (pJ) 242system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 243system.mem_ctrls_1.totalEnergy 5939616 # Total energy per rank (pJ) 244system.mem_ctrls_1.averagePower 429.752985 # Core power per rank (mW) 245system.mem_ctrls_1.totalIdleTime 0 # Total Idle time Per DRAM Rank |
| 237system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states 238system.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states | 246system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states 247system.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states |
| 239system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 248system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states 249system.mem_ctrls_1.memoryStateTime::PRE_PDN 5775 # Time in different power states |
| 240system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states 241system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 250system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states 251system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 242system.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 252system.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 243system.ruby.clk_domain.clock 1 # Clock period in ticks | 253system.ruby.clk_domain.clock 1 # Clock period in ticks |
| 244system.ruby.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 254system.ruby.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 245system.ruby.outstanding_req_hist_seqr::bucket_size 2 246system.ruby.outstanding_req_hist_seqr::max_bucket 19 247system.ruby.outstanding_req_hist_seqr::samples 63 | 255system.ruby.outstanding_req_hist_seqr::bucket_size 2 256system.ruby.outstanding_req_hist_seqr::max_bucket 19 257system.ruby.outstanding_req_hist_seqr::samples 63 |
| 248system.ruby.outstanding_req_hist_seqr::mean 12.920635 249system.ruby.outstanding_req_hist_seqr::gmean 11.694862 250system.ruby.outstanding_req_hist_seqr::stdev 4.228557 251system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 14 22.22% 57.14% | 27 42.86% 100.00% | 0 0.00% 100.00% | 258system.ruby.outstanding_req_hist_seqr::mean 12.873016 259system.ruby.outstanding_req_hist_seqr::gmean 11.658152 260system.ruby.outstanding_req_hist_seqr::stdev 4.202503 261system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 16 25.40% 60.32% | 25 39.68% 100.00% | 0 0.00% 100.00% |
| 252system.ruby.outstanding_req_hist_seqr::total 63 253system.ruby.outstanding_req_hist_coalsr::bucket_size 2 254system.ruby.outstanding_req_hist_coalsr::max_bucket 19 | 262system.ruby.outstanding_req_hist_seqr::total 63 263system.ruby.outstanding_req_hist_coalsr::bucket_size 2 264system.ruby.outstanding_req_hist_coalsr::max_bucket 19 |
| 255system.ruby.outstanding_req_hist_coalsr::samples 885 256system.ruby.outstanding_req_hist_coalsr::mean 2.610169 257system.ruby.outstanding_req_hist_coalsr::gmean 2.223354 258system.ruby.outstanding_req_hist_coalsr::stdev 1.538535 259system.ruby.outstanding_req_hist_coalsr | 219 24.75% 24.75% | 478 54.01% 78.76% | 135 15.25% 94.01% | 43 4.86% 98.87% | 9 1.02% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 260system.ruby.outstanding_req_hist_coalsr::total 885 | 265system.ruby.outstanding_req_hist_coalsr::samples 872 266system.ruby.outstanding_req_hist_coalsr::mean 2.547018 267system.ruby.outstanding_req_hist_coalsr::gmean 2.158955 268system.ruby.outstanding_req_hist_coalsr::stdev 1.537168 269system.ruby.outstanding_req_hist_coalsr | 236 27.06% 27.06% | 460 52.75% 79.82% | 126 14.45% 94.27% | 40 4.59% 98.85% | 9 1.03% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 270system.ruby.outstanding_req_hist_coalsr::total 872 |
| 261system.ruby.latency_hist_seqr::bucket_size 1024 262system.ruby.latency_hist_seqr::max_bucket 10239 263system.ruby.latency_hist_seqr::samples 48 | 271system.ruby.latency_hist_seqr::bucket_size 1024 272system.ruby.latency_hist_seqr::max_bucket 10239 273system.ruby.latency_hist_seqr::samples 48 |
| 264system.ruby.latency_hist_seqr::mean 3351.354167 265system.ruby.latency_hist_seqr::gmean 1865.352879 266system.ruby.latency_hist_seqr::stdev 1934.275107 267system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 18 37.50% 87.50% | 6 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 274system.ruby.latency_hist_seqr::mean 3315.854167 275system.ruby.latency_hist_seqr::gmean 1841.298781 276system.ruby.latency_hist_seqr::stdev 1907.716848 277system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 20 41.67% 91.67% | 4 8.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 268system.ruby.latency_hist_seqr::total 48 269system.ruby.latency_hist_coalsr::bucket_size 128 270system.ruby.latency_hist_coalsr::max_bucket 1279 | 278system.ruby.latency_hist_seqr::total 48 279system.ruby.latency_hist_coalsr::bucket_size 128 280system.ruby.latency_hist_coalsr::max_bucket 1279 |
| 271system.ruby.latency_hist_coalsr::samples 872 272system.ruby.latency_hist_coalsr::mean 222.089450 273system.ruby.latency_hist_coalsr::gmean 114.436171 274system.ruby.latency_hist_coalsr::stdev 241.512900 275system.ruby.latency_hist_coalsr | 580 66.51% 66.51% | 30 3.44% 69.95% | 110 12.61% 82.57% | 39 4.47% 87.04% | 33 3.78% 90.83% | 20 2.29% 93.12% | 33 3.78% 96.90% | 23 2.64% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% 276system.ruby.latency_hist_coalsr::total 872 | 281system.ruby.latency_hist_coalsr::samples 858 282system.ruby.latency_hist_coalsr::mean 215.358974 283system.ruby.latency_hist_coalsr::gmean 107.894342 284system.ruby.latency_hist_coalsr::stdev 237.470134 285system.ruby.latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00% 286system.ruby.latency_hist_coalsr::total 858 |
| 277system.ruby.hit_latency_hist_seqr::bucket_size 1024 278system.ruby.hit_latency_hist_seqr::max_bucket 10239 279system.ruby.hit_latency_hist_seqr::samples 42 | 287system.ruby.hit_latency_hist_seqr::bucket_size 1024 288system.ruby.hit_latency_hist_seqr::max_bucket 10239 289system.ruby.hit_latency_hist_seqr::samples 42 |
| 280system.ruby.hit_latency_hist_seqr::mean 3684.428571 281system.ruby.hit_latency_hist_seqr::gmean 2778.454716 282system.ruby.hit_latency_hist_seqr::stdev 1783.107224 283system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 290system.ruby.hit_latency_hist_seqr::mean 3644.142857 291system.ruby.hit_latency_hist_seqr::gmean 2737.850881 292system.ruby.hit_latency_hist_seqr::stdev 1757.652877 293system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 284system.ruby.hit_latency_hist_seqr::total 42 285system.ruby.miss_latency_hist_seqr::bucket_size 512 286system.ruby.miss_latency_hist_seqr::max_bucket 5119 287system.ruby.miss_latency_hist_seqr::samples 6 | 294system.ruby.hit_latency_hist_seqr::total 42 295system.ruby.miss_latency_hist_seqr::bucket_size 512 296system.ruby.miss_latency_hist_seqr::max_bucket 5119 297system.ruby.miss_latency_hist_seqr::samples 6 |
| 288system.ruby.miss_latency_hist_seqr::mean 1019.833333 289system.ruby.miss_latency_hist_seqr::gmean 114.673945 290system.ruby.miss_latency_hist_seqr::stdev 1281.644790 291system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 298system.ruby.miss_latency_hist_seqr::mean 1017.833333 299system.ruby.miss_latency_hist_seqr::gmean 114.584426 300system.ruby.miss_latency_hist_seqr::stdev 1278.753677 301system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 292system.ruby.miss_latency_hist_seqr::total 6 293system.ruby.miss_latency_hist_coalsr::bucket_size 128 294system.ruby.miss_latency_hist_coalsr::max_bucket 1279 | 302system.ruby.miss_latency_hist_seqr::total 6 303system.ruby.miss_latency_hist_coalsr::bucket_size 128 304system.ruby.miss_latency_hist_coalsr::max_bucket 1279 |
| 295system.ruby.miss_latency_hist_coalsr::samples 872 296system.ruby.miss_latency_hist_coalsr::mean 222.089450 297system.ruby.miss_latency_hist_coalsr::gmean 114.436171 298system.ruby.miss_latency_hist_coalsr::stdev 241.512900 299system.ruby.miss_latency_hist_coalsr | 580 66.51% 66.51% | 30 3.44% 69.95% | 110 12.61% 82.57% | 39 4.47% 87.04% | 33 3.78% 90.83% | 20 2.29% 93.12% | 33 3.78% 96.90% | 23 2.64% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% 300system.ruby.miss_latency_hist_coalsr::total 872 | 305system.ruby.miss_latency_hist_coalsr::samples 858 306system.ruby.miss_latency_hist_coalsr::mean 215.358974 307system.ruby.miss_latency_hist_coalsr::gmean 107.894342 308system.ruby.miss_latency_hist_coalsr::stdev 237.470134 309system.ruby.miss_latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00% 310system.ruby.miss_latency_hist_coalsr::total 858 |
| 301system.ruby.L1Cache.incomplete_times_seqr 6 302system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 303system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses 304system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses 305system.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes | 311system.ruby.L1Cache.incomplete_times_seqr 6 312system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 313system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses 314system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses 315system.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes |
| 306system.cp_cntrl0.L1D0cache.num_tag_array_reads 154 # number of tag array reads | 316system.cp_cntrl0.L1D0cache.num_tag_array_reads 155 # number of tag array reads |
| 307system.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes 308system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits | 317system.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes 318system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits |
| 309system.cp_cntrl0.L1D1cache.demand_misses 43 # Number of cache demand misses 310system.cp_cntrl0.L1D1cache.demand_accesses 43 # Number of cache demand accesses 311system.cp_cntrl0.L1D1cache.num_data_array_writes 41 # number of data array writes 312system.cp_cntrl0.L1D1cache.num_tag_array_reads 73 # number of tag array reads 313system.cp_cntrl0.L1D1cache.num_tag_array_writes 41 # number of tag array writes | 319system.cp_cntrl0.L1D1cache.demand_misses 45 # Number of cache demand misses 320system.cp_cntrl0.L1D1cache.demand_accesses 45 # Number of cache demand accesses 321system.cp_cntrl0.L1D1cache.num_data_array_writes 42 # number of data array writes 322system.cp_cntrl0.L1D1cache.num_tag_array_reads 74 # number of tag array reads 323system.cp_cntrl0.L1D1cache.num_tag_array_writes 42 # number of tag array writes |
| 314system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 315system.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses 316system.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses 317system.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads 318system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits | 324system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 325system.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses 326system.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses 327system.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads 328system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits |
| 319system.cp_cntrl0.L2cache.demand_misses 91 # Number of cache demand misses 320system.cp_cntrl0.L2cache.demand_accesses 91 # Number of cache demand accesses | 329system.cp_cntrl0.L2cache.demand_misses 93 # Number of cache demand misses 330system.cp_cntrl0.L2cache.demand_accesses 93 # Number of cache demand accesses |
| 321system.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads | 331system.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads |
| 322system.cp_cntrl0.L2cache.num_data_array_writes 84 # number of data array writes 323system.cp_cntrl0.L2cache.num_tag_array_reads 380 # number of tag array reads 324system.cp_cntrl0.L2cache.num_tag_array_writes 371 # number of tag array writes 325system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 326system.cp_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load 327system.cp_cntrl0.sequencer.store_waiting_on_store 3 # Number of times a store aliased with a pending store 328system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 329system.cp_cntrl0.sequencer1.store_waiting_on_load 1 # Number of times a store aliased with a pending load | 332system.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes 333system.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads 334system.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes 335system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 336system.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load 337system.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store 338system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 330system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store | 339system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store |
| 331system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 332system.cp_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions 333system.cpu.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 340system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 341system.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 334system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 335system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 336system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses | 342system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 343system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 344system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses |
| 337system.dir_cntrl0.L3CacheMemory.num_data_array_writes 374 # number of data array writes 338system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 378 # number of tag array reads 339system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 378 # number of tag array writes 340system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 10169 # number of stalls caused by tag array 341system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 5502 # number of stalls caused by data array 342system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 343system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 344system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199210 345system.ruby.network.ext_links00.int_node.msg_count.Control::0 308 346system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 385 347system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 393 348system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 227 349system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 66 350system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 70 351system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 303 352system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2464 353system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 3080 354system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 28296 355system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1816 356system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4752 357system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 560 358system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2424 359system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 360system.ruby.network.ext_links01.int_node.percent_links_utilized 0.120981 361system.ruby.network.ext_links01.int_node.msg_count.Control::0 227 362system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 153 | 345system.dir_cntrl0.L3CacheMemory.num_data_array_writes 365 # number of data array writes 346system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372 # number of tag array reads 347system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes 348system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array 349system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array 350system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 351system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 352system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915 353system.ruby.network.ext_links00.int_node.msg_count.Control::0 300 354system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 372 355system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 383 356system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 217 357system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 67 358system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 71 359system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 295 360system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2400 361system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 2976 362system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 27576 363system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1736 364system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824 365system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568 366system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360 367system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 368system.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680 369system.ruby.network.ext_links01.int_node.msg_count.Control::0 216 370system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 155 |
| 363system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95 | 371system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95 |
| 364system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 217 365system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 66 366system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 70 367system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 80 368system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1816 369system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1224 | 372system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 207 373system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 67 374system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 71 375system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 81 376system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1728 377system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1240 |
| 370system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840 | 378system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840 |
| 371system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1736 372system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4752 373system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 560 374system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 640 | 379system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1656 380system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4824 381system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 568 382system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 648 |
| 375system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 376system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 377system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses | 383system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 384system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 385system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 378system.tcp_cntrl0.L1cache.num_data_array_reads 14 # number of data array reads 379system.tcp_cntrl0.L1cache.num_data_array_writes 116 # number of data array writes 380system.tcp_cntrl0.L1cache.num_tag_array_reads 314 # number of tag array reads 381system.tcp_cntrl0.L1cache.num_tag_array_writes 305 # number of tag array writes 382system.tcp_cntrl0.L1cache.num_tag_array_stalls 38 # number of stalls caused by tag array 383system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 386system.tcp_cntrl0.L1cache.num_data_array_reads 16 # number of data array reads 387system.tcp_cntrl0.L1cache.num_data_array_writes 112 # number of data array writes 388system.tcp_cntrl0.L1cache.num_tag_array_reads 309 # number of tag array reads 389system.tcp_cntrl0.L1cache.num_tag_array_writes 300 # number of tag array writes 390system.tcp_cntrl0.L1cache.num_tag_array_stalls 28 # number of stalls caused by tag array 391system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 384system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP | 392system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP |
| 385system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers | 393system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers |
| 386system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC | 394system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC |
| 387system.tcp_cntrl0.coalescer.gpu_ld_misses 0 # loads that miss in the GPU | 395system.tcp_cntrl0.coalescer.gpu_ld_misses 1 # loads that miss in the GPU |
| 388system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP | 396system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP |
| 389system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 79 # TCP to TCP store transfers | 397system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers |
| 390system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 398system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 391system.tcp_cntrl0.coalescer.gpu_st_misses 21 # stores that miss in the GPU | 399system.tcp_cntrl0.coalescer.gpu_st_misses 19 # stores that miss in the GPU |
| 392system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 393system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 394system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 395system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 396system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 397system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 398system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 399system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU | 400system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 401system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 402system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 403system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 404system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 405system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 406system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 407system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 400system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 401system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 402system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 403system.ruby.network.ext_links02.int_node.percent_links_utilized 0.173894 404system.ruby.network.ext_links02.int_node.msg_count.Control::0 81 405system.ruby.network.ext_links02.int_node.msg_count.Control::1 814 406system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 232 407system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 846 408system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 298 409system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1644 | 408system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 409system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 410system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 411system.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944 412system.ruby.network.ext_links02.int_node.msg_count.Control::0 84 413system.ruby.network.ext_links02.int_node.msg_count.Control::1 789 414system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 217 415system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 823 416system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 288 417system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1594 |
| 410system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10 411system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2 | 418system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10 419system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2 |
| 412system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 223 413system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 831 414system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 648 415system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6512 416system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1856 417system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6768 418system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 21456 419system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 118368 | 420system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 214 421system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 810 422system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 672 423system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6312 424system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1736 425system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6584 426system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 20736 427system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 114768 |
| 420system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80 421system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16 | 428system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80 429system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16 |
| 422system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1784 423system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6648 | 430system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1712 431system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6480 |
| 424system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 425system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 426system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses | 432system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 433system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 434system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 427system.tcp_cntrl1.L1cache.num_data_array_reads 10 # number of data array reads | 435system.tcp_cntrl1.L1cache.num_data_array_reads 11 # number of data array reads |
| 428system.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes | 436system.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes |
| 429system.tcp_cntrl1.L1cache.num_tag_array_reads 300 # number of tag array reads 430system.tcp_cntrl1.L1cache.num_tag_array_writes 289 # number of tag array writes 431system.tcp_cntrl1.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array 432system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 437system.tcp_cntrl1.L1cache.num_tag_array_reads 298 # number of tag array reads 438system.tcp_cntrl1.L1cache.num_tag_array_writes 285 # number of tag array writes 439system.tcp_cntrl1.L1cache.num_tag_array_stalls 43 # number of stalls caused by tag array 440system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 433system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP | 441system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP |
| 434system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers | 442system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers |
| 435system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC | 443system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC |
| 436system.tcp_cntrl1.coalescer.gpu_ld_misses 1 # loads that miss in the GPU 437system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP 438system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers | 444system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 445system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 11 # stores that hit in the TCP 446system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers |
| 439system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 440system.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU 441system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 442system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 443system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 444system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 445system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 446system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 447system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 448system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU | 447system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 448system.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU 449system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 450system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 451system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 452system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 453system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 454system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 455system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 456system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 449system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 450system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 457system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 458system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 451system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits 452system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses 453system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses | 459system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits 460system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses 461system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 454system.tcp_cntrl2.L1cache.num_data_array_reads 19 # number of data array reads 455system.tcp_cntrl2.L1cache.num_data_array_writes 108 # number of data array writes 456system.tcp_cntrl2.L1cache.num_tag_array_reads 302 # number of tag array reads 457system.tcp_cntrl2.L1cache.num_tag_array_writes 292 # number of tag array writes 458system.tcp_cntrl2.L1cache.num_tag_array_stalls 36 # number of stalls caused by tag array 459system.tcp_cntrl2.L1cache.num_data_array_stalls 3 # number of stalls caused by data array 460system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 461system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP 462system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers | 462system.tcp_cntrl2.L1cache.num_data_array_reads 11 # number of data array reads 463system.tcp_cntrl2.L1cache.num_data_array_writes 106 # number of data array writes 464system.tcp_cntrl2.L1cache.num_tag_array_reads 286 # number of tag array reads 465system.tcp_cntrl2.L1cache.num_tag_array_writes 275 # number of tag array writes 466system.tcp_cntrl2.L1cache.num_tag_array_stalls 42 # number of stalls caused by tag array 467system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 468system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 469system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers |
| 463system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC | 470system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC |
| 464system.tcp_cntrl2.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 465system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP 466system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers | 471system.tcp_cntrl2.coalescer.gpu_ld_misses 1 # loads that miss in the GPU 472system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP 473system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers |
| 467system.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 468system.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU 469system.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 470system.tcp_cntrl2.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 471system.tcp_cntrl2.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 472system.tcp_cntrl2.coalescer.cp_ld_misses 0 # loads that miss in the GPU 473system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 474system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 475system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 476system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU | 474system.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 475system.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU 476system.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 477system.tcp_cntrl2.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 478system.tcp_cntrl2.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 479system.tcp_cntrl2.coalescer.cp_ld_misses 0 # loads that miss in the GPU 480system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 481system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 482system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 483system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 477system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 478system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 484system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 485system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 479system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits 480system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses 481system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses | 486system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits 487system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses 488system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 482system.tcp_cntrl3.L1cache.num_data_array_reads 7 # number of data array reads 483system.tcp_cntrl3.L1cache.num_data_array_writes 104 # number of data array writes 484system.tcp_cntrl3.L1cache.num_tag_array_reads 272 # number of tag array reads 485system.tcp_cntrl3.L1cache.num_tag_array_writes 262 # number of tag array writes 486system.tcp_cntrl3.L1cache.num_tag_array_stalls 16 # number of stalls caused by tag array | 489system.tcp_cntrl3.L1cache.num_data_array_reads 8 # number of data array reads 490system.tcp_cntrl3.L1cache.num_data_array_writes 95 # number of data array writes 491system.tcp_cntrl3.L1cache.num_tag_array_reads 260 # number of tag array reads 492system.tcp_cntrl3.L1cache.num_tag_array_writes 253 # number of tag array writes 493system.tcp_cntrl3.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array |
| 487system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array | 494system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array |
| 488system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 495system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 489system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP | 496system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP |
| 490system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 13 # TCP to TCP load transfers | 497system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 12 # TCP to TCP load transfers |
| 491system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 492system.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU | 498system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 499system.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU |
| 493system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 10 # stores that hit in the TCP 494system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 63 # TCP to TCP store transfers | 500system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP 501system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 59 # TCP to TCP store transfers |
| 495system.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 502system.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 496system.tcp_cntrl3.coalescer.gpu_st_misses 18 # stores that miss in the GPU | 503system.tcp_cntrl3.coalescer.gpu_st_misses 17 # stores that miss in the GPU |
| 497system.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 498system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 499system.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 500system.tcp_cntrl3.coalescer.cp_ld_misses 0 # loads that miss in the GPU 501system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 502system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 503system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 504system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU | 504system.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 505system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 506system.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 507system.tcp_cntrl3.coalescer.cp_ld_misses 0 # loads that miss in the GPU 508system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 509system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 510system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 511system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 505system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 506system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 512system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 513system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 507system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits 508system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses 509system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses | 514system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits 515system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses 516system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 510system.tcp_cntrl4.L1cache.num_data_array_reads 14 # number of data array reads 511system.tcp_cntrl4.L1cache.num_data_array_writes 115 # number of data array writes 512system.tcp_cntrl4.L1cache.num_tag_array_reads 317 # number of tag array reads 513system.tcp_cntrl4.L1cache.num_tag_array_writes 309 # number of tag array writes 514system.tcp_cntrl4.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array 515system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 516system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 517system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers | 517system.tcp_cntrl4.L1cache.num_data_array_reads 16 # number of data array reads 518system.tcp_cntrl4.L1cache.num_data_array_writes 117 # number of data array writes 519system.tcp_cntrl4.L1cache.num_tag_array_reads 309 # number of tag array reads 520system.tcp_cntrl4.L1cache.num_tag_array_writes 299 # number of tag array writes 521system.tcp_cntrl4.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array 522system.tcp_cntrl4.L1cache.num_data_array_stalls 4 # number of stalls caused by data array 523system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 524system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP 525system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers |
| 518system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 519system.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU | 526system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 527system.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU |
| 520system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 6 # stores that hit in the TCP 521system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 76 # TCP to TCP store transfers | 528system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP 529system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers |
| 522system.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 523system.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU 524system.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 525system.tcp_cntrl4.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 526system.tcp_cntrl4.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 527system.tcp_cntrl4.coalescer.cp_ld_misses 0 # loads that miss in the GPU 528system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 529system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 530system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 531system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU | 530system.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 531system.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU 532system.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 533system.tcp_cntrl4.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 534system.tcp_cntrl4.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 535system.tcp_cntrl4.coalescer.cp_ld_misses 0 # loads that miss in the GPU 536system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 537system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 538system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 539system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 532system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 533system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 540system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 541system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 534system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits 535system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses 536system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses | 542system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits 543system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses 544system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 537system.tcp_cntrl5.L1cache.num_data_array_reads 10 # number of data array reads 538system.tcp_cntrl5.L1cache.num_data_array_writes 107 # number of data array writes 539system.tcp_cntrl5.L1cache.num_tag_array_reads 295 # number of tag array reads 540system.tcp_cntrl5.L1cache.num_tag_array_writes 287 # number of tag array writes 541system.tcp_cntrl5.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array 542system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 545system.tcp_cntrl5.L1cache.num_data_array_reads 9 # number of data array reads 546system.tcp_cntrl5.L1cache.num_data_array_writes 101 # number of data array writes 547system.tcp_cntrl5.L1cache.num_tag_array_reads 276 # number of tag array reads 548system.tcp_cntrl5.L1cache.num_tag_array_writes 266 # number of tag array writes 549system.tcp_cntrl5.L1cache.num_tag_array_stalls 22 # number of stalls caused by tag array 550system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 543system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP | 551system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP |
| 544system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 6 # TCP to TCP load transfers | 552system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 3 # TCP to TCP load transfers |
| 545system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 546system.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 547system.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP | 553system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 554system.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 555system.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP |
| 548system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers | 556system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 67 # TCP to TCP store transfers |
| 549system.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 557system.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 550system.tcp_cntrl5.coalescer.gpu_st_misses 23 # stores that miss in the GPU | 558system.tcp_cntrl5.coalescer.gpu_st_misses 22 # stores that miss in the GPU |
| 551system.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 552system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 553system.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 554system.tcp_cntrl5.coalescer.cp_ld_misses 0 # loads that miss in the GPU 555system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 556system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 557system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 558system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU | 559system.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 560system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 561system.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 562system.tcp_cntrl5.coalescer.cp_ld_misses 0 # loads that miss in the GPU 563system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 564system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 565system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 566system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 559system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 560system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 567system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 568system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 561system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits 562system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses 563system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses | 569system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits 570system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses 571system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 564system.tcp_cntrl6.L1cache.num_data_array_reads 13 # number of data array reads 565system.tcp_cntrl6.L1cache.num_data_array_writes 123 # number of data array writes 566system.tcp_cntrl6.L1cache.num_tag_array_reads 342 # number of tag array reads 567system.tcp_cntrl6.L1cache.num_tag_array_writes 335 # number of tag array writes 568system.tcp_cntrl6.L1cache.num_tag_array_stalls 49 # number of stalls caused by tag array 569system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 572system.tcp_cntrl6.L1cache.num_data_array_reads 15 # number of data array reads 573system.tcp_cntrl6.L1cache.num_data_array_writes 120 # number of data array writes 574system.tcp_cntrl6.L1cache.num_tag_array_reads 336 # number of tag array reads 575system.tcp_cntrl6.L1cache.num_tag_array_writes 330 # number of tag array writes 576system.tcp_cntrl6.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array 577system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 570system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP | 578system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP |
| 571system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 11 # TCP to TCP load transfers | 579system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers |
| 572system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 573system.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU | 580system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 581system.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU |
| 574system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 5 # stores that hit in the TCP | 582system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP |
| 575system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers 576system.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 583system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers 584system.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 577system.tcp_cntrl6.coalescer.gpu_st_misses 19 # stores that miss in the GPU | 585system.tcp_cntrl6.coalescer.gpu_st_misses 20 # stores that miss in the GPU |
| 578system.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 579system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 580system.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 581system.tcp_cntrl6.coalescer.cp_ld_misses 0 # loads that miss in the GPU 582system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 583system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 584system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 585system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU | 586system.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 587system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 588system.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 589system.tcp_cntrl6.coalescer.cp_ld_misses 0 # loads that miss in the GPU 590system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 591system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 592system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 593system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 586system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 587system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 594system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 595system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 588system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits 589system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses 590system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses | 596system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits 597system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses 598system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 591system.tcp_cntrl7.L1cache.num_data_array_reads 10 # number of data array reads 592system.tcp_cntrl7.L1cache.num_data_array_writes 97 # number of data array writes 593system.tcp_cntrl7.L1cache.num_tag_array_reads 263 # number of tag array reads 594system.tcp_cntrl7.L1cache.num_tag_array_writes 256 # number of tag array writes | 599system.tcp_cntrl7.L1cache.num_data_array_reads 13 # number of data array reads 600system.tcp_cntrl7.L1cache.num_data_array_writes 101 # number of data array writes 601system.tcp_cntrl7.L1cache.num_tag_array_reads 275 # number of tag array reads 602system.tcp_cntrl7.L1cache.num_tag_array_writes 266 # number of tag array writes |
| 595system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array | 603system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array |
| 596system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 597system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP 598system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 10 # TCP to TCP load transfers | 604system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 605system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 606system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers |
| 599system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC | 607system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC |
| 600system.tcp_cntrl7.coalescer.gpu_ld_misses 1 # loads that miss in the GPU 601system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 6 # stores that hit in the TCP 602system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 63 # TCP to TCP store transfers | 608system.tcp_cntrl7.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 609system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP 610system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 66 # TCP to TCP store transfers |
| 603system.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC | 611system.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC |
| 604system.tcp_cntrl7.coalescer.gpu_st_misses 16 # stores that miss in the GPU | 612system.tcp_cntrl7.coalescer.gpu_st_misses 18 # stores that miss in the GPU |
| 605system.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 606system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 607system.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 608system.tcp_cntrl7.coalescer.cp_ld_misses 0 # loads that miss in the GPU 609system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 610system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 611system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 612system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU | 613system.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 614system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 615system.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 616system.tcp_cntrl7.coalescer.cp_ld_misses 0 # loads that miss in the GPU 617system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 618system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 619system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 620system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU |
| 613system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 614system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 621system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 622system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 615system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 616system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 617system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 618system.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads 619system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes | 623system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 624system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 625system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 626system.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads 627system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes |
| 620system.sqc_cntrl0.L1cache.num_tag_array_reads 22 # number of tag array reads 621system.sqc_cntrl0.L1cache.num_tag_array_writes 22 # number of tag array writes 622system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 623system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 628system.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads 629system.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes 630system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 631system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 624system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 625system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 626system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses | 632system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 633system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 634system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses |
| 627system.sqc_cntrl1.L1cache.num_data_array_reads 15 # number of data array reads 628system.sqc_cntrl1.L1cache.num_data_array_writes 15 # number of data array writes 629system.sqc_cntrl1.L1cache.num_tag_array_reads 29 # number of tag array reads 630system.sqc_cntrl1.L1cache.num_tag_array_writes 29 # number of tag array writes 631system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 632system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 635system.sqc_cntrl1.L1cache.num_data_array_reads 12 # number of data array reads 636system.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes 637system.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads 638system.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes 639system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 640system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 633system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 634system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 635system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses | 641system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 642system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 643system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses |
| 636system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states | 644system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states |
| 637system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 638system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 639system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses | 645system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 646system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 647system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses |
| 640system.tccdir_cntrl0.directory.num_tag_array_reads 917 # number of tag array reads 641system.tccdir_cntrl0.directory.num_tag_array_writes 902 # number of tag array writes 642system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 643system.ruby.network.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 644system.ruby.network.msg_count.Control 1430 645system.ruby.network.msg_count.Request_Control 1616 646system.ruby.network.msg_count.Response_Data 2430 647system.ruby.network.msg_count.Response_Control 456 648system.ruby.network.msg_count.Writeback_Data 132 649system.ruby.network.msg_count.Writeback_Control 140 650system.ruby.network.msg_count.Unblock_Control 1437 651system.ruby.network.msg_byte.Control 11440 652system.ruby.network.msg_byte.Request_Control 12928 653system.ruby.network.msg_byte.Response_Data 174960 654system.ruby.network.msg_byte.Response_Control 3648 655system.ruby.network.msg_byte.Writeback_Data 9504 656system.ruby.network.msg_byte.Writeback_Control 1120 657system.ruby.network.msg_byte.Unblock_Control 11496 658system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states 659system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.250555 660system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 385 | 648system.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads 649system.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes 650system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 651system.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 652system.ruby.network.msg_count.Control 1389 653system.ruby.network.msg_count.Request_Control 1567 654system.ruby.network.msg_count.Response_Data 2360 655system.ruby.network.msg_count.Response_Control 436 656system.ruby.network.msg_count.Writeback_Data 134 657system.ruby.network.msg_count.Writeback_Control 142 658system.ruby.network.msg_count.Unblock_Control 1400 659system.ruby.network.msg_byte.Control 11112 660system.ruby.network.msg_byte.Request_Control 12536 661system.ruby.network.msg_byte.Response_Data 169920 662system.ruby.network.msg_byte.Response_Control 3488 663system.ruby.network.msg_byte.Writeback_Data 9648 664system.ruby.network.msg_byte.Writeback_Control 1136 665system.ruby.network.msg_byte.Unblock_Control 11200 666system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 667system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.254594 668system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 372 |
| 661system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85 | 669system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85 |
| 662system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 227 663system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 66 664system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 303 665system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 3080 | 670system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 217 671system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 67 672system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 295 673system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 2976 |
| 666system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120 | 674system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120 |
| 667system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1816 668system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4752 669system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2424 670system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.113047 671system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 227 672system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 81 673system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 70 674system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1816 675system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5832 676system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 560 677system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.234028 678system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 81 679system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 227 680system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 648 681system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 16344 682system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.113047 683system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 227 684system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 81 685system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 70 686system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1816 687system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5832 688system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 560 689system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.128914 690system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 153 691system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 14 692system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 217 693system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 66 694system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 80 695system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1224 696system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 1008 697system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1736 698system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4752 699system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 640 700system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.115361 701system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 102 702system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 105 703system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 816 704system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7560 705system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.108750 706system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 96 707system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 99 708system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 768 709system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 7128 710system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.109742 711system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 105 712system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 99 713system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 840 714system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 7128 715system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.102690 | 675system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1736 676system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4824 677system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2360 678system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.115879 679system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 216 680system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 82 681system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 71 682system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1728 683system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5904 684system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 568 685system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.229271 686system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 84 687system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 216 688system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 672 689system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 15552 690system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.115879 691system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 216 692system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 82 693system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 71 694system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1728 695system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5904 696system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 568 697system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.131480 698system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 155 699system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 13 700system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 207 701system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 67 702system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 81 703system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1240 704system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 936 705system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1656 706system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4824 707system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 648 708system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.116105 709system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 100 710system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 103 711system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 800 712system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7416 713system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.109661 714system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 97 715system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 97 716system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 776 717system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 6984 718system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.108078 719system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 92 720system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 96 721system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 736 722system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 6912 723system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.099260 |
| 716system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86 | 724system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86 |
| 717system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 94 | 725system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 88 |
| 718system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688 | 726system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688 |
| 719system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6768 720system.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116573 | 727system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6336 728system.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116557 |
| 721system.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1 104 | 729system.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1 104 |
| 722system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3 106 | 730system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3 103 |
| 723system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1 832 | 731system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1 832 |
| 724system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7632 725system.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.107759 726system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 96 727system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 98 728system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 768 729system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 7056 730system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.128473 731system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 113 732system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 117 733system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 904 734system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8424 735system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.098944 736system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 88 737system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 90 738system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 704 739system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6480 | 732system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7416 733system.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.103556 734system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 88 735system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 92 736system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 704 737system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 6624 738system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.129558 739system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 111 740system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 115 741system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 888 742system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8280 743system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.104687 744system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 89 745system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 93 746system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 712 747system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6696 |
| 740system.ruby.network.ext_links02.int_node.throttle8.link_utilization 0 | 748system.ruby.network.ext_links02.int_node.throttle8.link_utilization 0 |
| 741system.ruby.network.ext_links02.int_node.throttle9.link_utilization 1.221264 742system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0 81 743system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1 846 744system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2 227 745system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3 809 | 749system.ruby.network.ext_links02.int_node.throttle9.link_utilization 1.210793 750system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0 84 751system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1 823 752system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2 216 753system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3 783 |
| 746system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3 2 | 754system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3 2 |
| 747system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5 831 748system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0 648 749system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1 6768 750system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2 16344 751system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3 58248 | 755system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5 810 756system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0 672 757system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1 6584 758system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2 15552 759system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3 56376 |
| 752system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16 | 760system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16 |
| 753system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6648 754system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013002 755system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 10 | 761system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6480 762system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013453 763system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 11 |
| 756system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12 | 764system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12 |
| 757system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 80 | 765system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 88 |
| 758system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864 | 766system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864 |
| 759system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.016417 760system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 14 761system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 15 762system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 112 763system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 1080 764system.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.121642 765system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 232 766system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 71 | 767system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.013453 768system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 11 769system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 12 770system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 88 771system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 864 772system.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.123114 773system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 217 774system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 72 |
| 767system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2 10 | 775system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2 10 |
| 768system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4 223 769system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0 1856 770system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2 5112 | 776system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4 214 777system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0 1736 778system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2 5184 |
| 771system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2 80 | 779system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2 80 |
| 772system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4 1784 | 780system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4 1712 |
| 773system.ruby.CorePair_Controller.C0_Load_L1miss 1 0.00% 0.00% | 781system.ruby.CorePair_Controller.C0_Load_L1miss 1 0.00% 0.00% |
| 774system.ruby.CorePair_Controller.C1_Load_L1miss 1 0.00% 0.00% | 782system.ruby.CorePair_Controller.C1_Load_L1miss 2 0.00% 0.00% |
| 775system.ruby.CorePair_Controller.Ifetch0_L1miss 2 0.00% 0.00% 776system.ruby.CorePair_Controller.Ifetch1_L1miss 1 0.00% 0.00% 777system.ruby.CorePair_Controller.C0_Store_L1miss 45 0.00% 0.00% 778system.ruby.CorePair_Controller.C0_Store_L1hit 2 0.00% 0.00% | 783system.ruby.CorePair_Controller.Ifetch0_L1miss 2 0.00% 0.00% 784system.ruby.CorePair_Controller.Ifetch1_L1miss 1 0.00% 0.00% 785system.ruby.CorePair_Controller.C0_Store_L1miss 45 0.00% 0.00% 786system.ruby.CorePair_Controller.C0_Store_L1hit 2 0.00% 0.00% |
| 779system.ruby.CorePair_Controller.C1_Store_L1miss 73 0.00% 0.00% | 787system.ruby.CorePair_Controller.C1_Store_L1miss 72 0.00% 0.00% |
| 780system.ruby.CorePair_Controller.NB_AckS 4 0.00% 0.00% | 788system.ruby.CorePair_Controller.NB_AckS 4 0.00% 0.00% |
| 781system.ruby.CorePair_Controller.NB_AckM 77 0.00% 0.00% 782system.ruby.CorePair_Controller.NB_AckWB 70 0.00% 0.00% 783system.ruby.CorePair_Controller.L1D0_Repl 19 0.00% 0.00% 784system.ruby.CorePair_Controller.L2_Repl 36624 0.00% 0.00% 785system.ruby.CorePair_Controller.PrbInvData 223 0.00% 0.00% | 789system.ruby.CorePair_Controller.NB_AckM 78 0.00% 0.00% 790system.ruby.CorePair_Controller.NB_AckWB 71 0.00% 0.00% 791system.ruby.CorePair_Controller.L1D0_Repl 11 0.00% 0.00% 792system.ruby.CorePair_Controller.L2_Repl 35555 0.00% 0.00% 793system.ruby.CorePair_Controller.PrbInvData 212 0.00% 0.00% |
| 786system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% 787system.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00% | 794system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% 795system.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00% |
| 788system.ruby.CorePair_Controller.I.C1_Load_L1miss 1 0.00% 0.00% | 796system.ruby.CorePair_Controller.I.C1_Load_L1miss 2 0.00% 0.00% |
| 789system.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00% 790system.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00% 791system.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00% | 797system.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00% 798system.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00% 799system.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00% |
| 792system.ruby.CorePair_Controller.I.C1_Store_L1miss 37 0.00% 0.00% 793system.ruby.CorePair_Controller.I.PrbInvData 209 0.00% 0.00% 794system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% | 800system.ruby.CorePair_Controller.I.C1_Store_L1miss 38 0.00% 0.00% 801system.ruby.CorePair_Controller.I.PrbInvData 198 0.00% 0.00% 802system.ruby.CorePair_Controller.I.PrbShrData 4 0.00% 0.00% |
| 795system.ruby.CorePair_Controller.S.L2_Repl 3 0.00% 0.00% 796system.ruby.CorePair_Controller.S.PrbInvData 1 0.00% 0.00% | 803system.ruby.CorePair_Controller.S.L2_Repl 3 0.00% 0.00% 804system.ruby.CorePair_Controller.S.PrbInvData 1 0.00% 0.00% |
| 797system.ruby.CorePair_Controller.O.PrbInvData 1 0.00% 0.00% | |
| 798system.ruby.CorePair_Controller.M0.C0_Store_L1hit 2 0.00% 0.00% 799system.ruby.CorePair_Controller.M0.L2_Repl 33 0.00% 0.00% | 805system.ruby.CorePair_Controller.M0.C0_Store_L1hit 2 0.00% 0.00% 806system.ruby.CorePair_Controller.M0.L2_Repl 33 0.00% 0.00% |
| 800system.ruby.CorePair_Controller.M0.PrbInvData 5 0.00% 0.00% 801system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% | 807system.ruby.CorePair_Controller.M0.PrbInvData 6 0.00% 0.00% |
| 802system.ruby.CorePair_Controller.M1.C0_Store_L1miss 1 0.00% 0.00% 803system.ruby.CorePair_Controller.M1.L2_Repl 36 0.00% 0.00% | 808system.ruby.CorePair_Controller.M1.C0_Store_L1miss 1 0.00% 0.00% 809system.ruby.CorePair_Controller.M1.L2_Repl 36 0.00% 0.00% |
| 804system.ruby.CorePair_Controller.M1.PrbInvData 2 0.00% 0.00% | 810system.ruby.CorePair_Controller.M1.PrbInvData 3 0.00% 0.00% |
| 805system.ruby.CorePair_Controller.I_M0.C1_Store_L1miss 5 0.00% 0.00% 806system.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00% 807system.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00% | 811system.ruby.CorePair_Controller.I_M0.C1_Store_L1miss 5 0.00% 0.00% 812system.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00% 813system.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00% |
| 808system.ruby.CorePair_Controller.I_M0.L2_Repl 16208 0.00% 0.00% | 814system.ruby.CorePair_Controller.I_M0.L2_Repl 15350 0.00% 0.00% |
| 809system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00% | 815system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00% |
| 810system.ruby.CorePair_Controller.I_M1.NB_AckM 34 0.00% 0.00% 811system.ruby.CorePair_Controller.I_M1.L2_Repl 14782 0.00% 0.00% | 816system.ruby.CorePair_Controller.I_M1.NB_AckM 35 0.00% 0.00% 817system.ruby.CorePair_Controller.I_M1.L2_Repl 14410 0.00% 0.00% |
| 812system.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00% | 818system.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00% |
| 813system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3020 0.00% 0.00% | 819system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3283 0.00% 0.00% |
| 814system.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00% | 820system.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00% |
| 815system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1059 0.00% 0.00% | 821system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1200 0.00% 0.00% |
| 816system.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00% | 822system.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00% |
| 817system.ruby.CorePair_Controller.I_E0S.L1D0_Repl 8 0.00% 0.00% 818system.ruby.CorePair_Controller.I_E0S.L2_Repl 493 0.00% 0.00% | 823system.ruby.CorePair_Controller.I_E0S.L2_Repl 404 0.00% 0.00% |
| 819system.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00% | 824system.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00% |
| 820system.ruby.CorePair_Controller.I_E1S.L2_Repl 638 0.00% 0.00% | 825system.ruby.CorePair_Controller.I_E1S.L2_Repl 392 0.00% 0.00% |
| 821system.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00% | 826system.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00% |
| 822system.ruby.CorePair_Controller.MO_I.NB_AckWB 64 0.00% 0.00% 823system.ruby.CorePair_Controller.MO_I.PrbInvData 5 0.00% 0.00% 824system.ruby.CorePair_Controller.S0.C1_Store_L1miss 31 0.00% 0.00% | 827system.ruby.CorePair_Controller.MO_I.NB_AckWB 65 0.00% 0.00% 828system.ruby.CorePair_Controller.MO_I.PrbInvData 4 0.00% 0.00% 829system.ruby.CorePair_Controller.S0.C1_Store_L1miss 29 0.00% 0.00% |
| 825system.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00% | 830system.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00% |
| 826system.ruby.CorePair_Controller.S0.L2_Repl 352 0.00% 0.00% | 831system.ruby.CorePair_Controller.S0.L2_Repl 444 0.00% 0.00% |
| 827system.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00% 828system.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00% | 832system.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00% 833system.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00% |
| 829system.ruby.Directory_Controller.RdBlkS 3 0.00% 0.00% 830system.ruby.Directory_Controller.RdBlkM 309 0.00% 0.00% | 834system.ruby.Directory_Controller.RdBlkS 4 0.00% 0.00% 835system.ruby.Directory_Controller.RdBlkM 297 0.00% 0.00% |
| 831system.ruby.Directory_Controller.RdBlk 6 0.00% 0.00% | 836system.ruby.Directory_Controller.RdBlk 6 0.00% 0.00% |
| 832system.ruby.Directory_Controller.VicDirty 68 0.00% 0.00% | 837system.ruby.Directory_Controller.VicDirty 69 0.00% 0.00% |
| 833system.ruby.Directory_Controller.VicClean 2 0.00% 0.00% | 838system.ruby.Directory_Controller.VicClean 2 0.00% 0.00% |
| 834system.ruby.Directory_Controller.CPUData 66 0.00% 0.00% | 839system.ruby.Directory_Controller.CPUData 67 0.00% 0.00% |
| 835system.ruby.Directory_Controller.StaleWB 4 0.00% 0.00% | 840system.ruby.Directory_Controller.StaleWB 4 0.00% 0.00% |
| 836system.ruby.Directory_Controller.CPUPrbResp 308 0.00% 0.00% 837system.ruby.Directory_Controller.ProbeAcksComplete 308 0.00% 0.00% 838system.ruby.Directory_Controller.L3Hit 49 0.00% 0.00% 839system.ruby.Directory_Controller.MemData 259 0.00% 0.00% 840system.ruby.Directory_Controller.WBAck 9 0.00% 0.00% 841system.ruby.Directory_Controller.CoreUnblock 303 0.00% 0.00% 842system.ruby.Directory_Controller.U.RdBlkS 3 0.00% 0.00% 843system.ruby.Directory_Controller.U.RdBlkM 300 0.00% 0.00% 844system.ruby.Directory_Controller.U.RdBlk 5 0.00% 0.00% 845system.ruby.Directory_Controller.U.VicDirty 68 0.00% 0.00% | 841system.ruby.Directory_Controller.CPUPrbResp 298 0.00% 0.00% 842system.ruby.Directory_Controller.ProbeAcksComplete 298 0.00% 0.00% 843system.ruby.Directory_Controller.L3Hit 45 0.00% 0.00% 844system.ruby.Directory_Controller.MemData 256 0.00% 0.00% 845system.ruby.Directory_Controller.WBAck 14 0.00% 0.00% 846system.ruby.Directory_Controller.CoreUnblock 295 0.00% 0.00% 847system.ruby.Directory_Controller.U.RdBlkS 4 0.00% 0.00% 848system.ruby.Directory_Controller.U.RdBlkM 291 0.00% 0.00% 849system.ruby.Directory_Controller.U.RdBlk 6 0.00% 0.00% 850system.ruby.Directory_Controller.U.VicDirty 69 0.00% 0.00% |
| 846system.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00% | 851system.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00% |
| 847system.ruby.Directory_Controller.U.WBAck 9 0.00% 0.00% 848system.ruby.Directory_Controller.BL.RdBlkM 1 0.00% 0.00% 849system.ruby.Directory_Controller.BL.CPUData 66 0.00% 0.00% | 852system.ruby.Directory_Controller.U.WBAck 14 0.00% 0.00% 853system.ruby.Directory_Controller.BL.CPUData 67 0.00% 0.00% |
| 850system.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00% | 854system.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00% |
| 851system.ruby.Directory_Controller.BM_M.MemData 8 0.00% 0.00% | 855system.ruby.Directory_Controller.BM_M.MemData 9 0.00% 0.00% |
| 852system.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00% | 856system.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00% |
| 853system.ruby.Directory_Controller.BS_PM.MemData 2 0.00% 0.00% | 857system.ruby.Directory_Controller.BS_PM.MemData 3 0.00% 0.00% |
| 854system.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00% | 858system.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00% |
| 855system.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00% 856system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 8 0.00% 0.00% 857system.ruby.Directory_Controller.BM_PM.L3Hit 46 0.00% 0.00% 858system.ruby.Directory_Controller.BM_PM.MemData 246 0.00% 0.00% 859system.ruby.Directory_Controller.B_PM.L3Hit 2 0.00% 0.00% | 859system.ruby.Directory_Controller.BM_PM.CPUPrbResp 13 0.00% 0.00% 860system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 9 0.00% 0.00% 861system.ruby.Directory_Controller.BM_PM.L3Hit 41 0.00% 0.00% 862system.ruby.Directory_Controller.BM_PM.MemData 241 0.00% 0.00% 863system.ruby.Directory_Controller.B_PM.L3Hit 3 0.00% 0.00% |
| 860system.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00% 861system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00% 862system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00% 863system.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00% | 864system.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00% 865system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00% 866system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00% 867system.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00% |
| 864system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 288 0.00% 0.00% 865system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 292 0.00% 0.00% | 868system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 277 0.00% 0.00% 869system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 281 0.00% 0.00% |
| 866system.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00% 867system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00% | 870system.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00% 871system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00% |
| 868system.ruby.Directory_Controller.B.RdBlkM 4 0.00% 0.00% 869system.ruby.Directory_Controller.B.RdBlk 1 0.00% 0.00% 870system.ruby.Directory_Controller.B.CoreUnblock 303 0.00% 0.00% | 872system.ruby.Directory_Controller.B.RdBlkM 2 0.00% 0.00% 873system.ruby.Directory_Controller.B.CoreUnblock 295 0.00% 0.00% |
| 871system.ruby.LD.latency_hist_seqr::bucket_size 1024 872system.ruby.LD.latency_hist_seqr::max_bucket 10239 873system.ruby.LD.latency_hist_seqr::samples 1 | 874system.ruby.LD.latency_hist_seqr::bucket_size 1024 875system.ruby.LD.latency_hist_seqr::max_bucket 10239 876system.ruby.LD.latency_hist_seqr::samples 1 |
| 874system.ruby.LD.latency_hist_seqr::mean 5324 875system.ruby.LD.latency_hist_seqr::gmean 5324.000000 | 877system.ruby.LD.latency_hist_seqr::mean 5256 878system.ruby.LD.latency_hist_seqr::gmean 5256.000000 |
| 876system.ruby.LD.latency_hist_seqr::stdev nan 877system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 878system.ruby.LD.latency_hist_seqr::total 1 | 879system.ruby.LD.latency_hist_seqr::stdev nan 880system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 881system.ruby.LD.latency_hist_seqr::total 1 |
| 879system.ruby.LD.latency_hist_coalsr::bucket_size 128 880system.ruby.LD.latency_hist_coalsr::max_bucket 1279 881system.ruby.LD.latency_hist_coalsr::samples 69 882system.ruby.LD.latency_hist_coalsr::mean 111.289855 883system.ruby.LD.latency_hist_coalsr::gmean 81.460116 884system.ruby.LD.latency_hist_coalsr::stdev 88.701101 885system.ruby.LD.latency_hist_coalsr | 63 91.30% 91.30% | 2 2.90% 94.20% | 2 2.90% 97.10% | 1 1.45% 98.55% | 0 0.00% 98.55% | 1 1.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 886system.ruby.LD.latency_hist_coalsr::total 69 | 882system.ruby.LD.latency_hist_coalsr::bucket_size 64 883system.ruby.LD.latency_hist_coalsr::max_bucket 639 884system.ruby.LD.latency_hist_coalsr::samples 72 885system.ruby.LD.latency_hist_coalsr::mean 101.402778 886system.ruby.LD.latency_hist_coalsr::gmean 68.071118 887system.ruby.LD.latency_hist_coalsr::stdev 67.272969 888system.ruby.LD.latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 889system.ruby.LD.latency_hist_coalsr::total 72 |
| 887system.ruby.LD.hit_latency_hist_seqr::bucket_size 1024 888system.ruby.LD.hit_latency_hist_seqr::max_bucket 10239 889system.ruby.LD.hit_latency_hist_seqr::samples 1 | 890system.ruby.LD.hit_latency_hist_seqr::bucket_size 1024 891system.ruby.LD.hit_latency_hist_seqr::max_bucket 10239 892system.ruby.LD.hit_latency_hist_seqr::samples 1 |
| 890system.ruby.LD.hit_latency_hist_seqr::mean 5324 891system.ruby.LD.hit_latency_hist_seqr::gmean 5324.000000 | 893system.ruby.LD.hit_latency_hist_seqr::mean 5256 894system.ruby.LD.hit_latency_hist_seqr::gmean 5256.000000 |
| 892system.ruby.LD.hit_latency_hist_seqr::stdev nan 893system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 894system.ruby.LD.hit_latency_hist_seqr::total 1 | 895system.ruby.LD.hit_latency_hist_seqr::stdev nan 896system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 897system.ruby.LD.hit_latency_hist_seqr::total 1 |
| 895system.ruby.LD.miss_latency_hist_coalsr::bucket_size 128 896system.ruby.LD.miss_latency_hist_coalsr::max_bucket 1279 897system.ruby.LD.miss_latency_hist_coalsr::samples 69 898system.ruby.LD.miss_latency_hist_coalsr::mean 111.289855 899system.ruby.LD.miss_latency_hist_coalsr::gmean 81.460116 900system.ruby.LD.miss_latency_hist_coalsr::stdev 88.701101 901system.ruby.LD.miss_latency_hist_coalsr | 63 91.30% 91.30% | 2 2.90% 94.20% | 2 2.90% 97.10% | 1 1.45% 98.55% | 0 0.00% 98.55% | 1 1.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 902system.ruby.LD.miss_latency_hist_coalsr::total 69 | 898system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 899system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 900system.ruby.LD.miss_latency_hist_coalsr::samples 72 901system.ruby.LD.miss_latency_hist_coalsr::mean 101.402778 902system.ruby.LD.miss_latency_hist_coalsr::gmean 68.071118 903system.ruby.LD.miss_latency_hist_coalsr::stdev 67.272969 904system.ruby.LD.miss_latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 905system.ruby.LD.miss_latency_hist_coalsr::total 72 |
| 903system.ruby.ST.latency_hist_seqr::bucket_size 1024 904system.ruby.ST.latency_hist_seqr::max_bucket 10239 905system.ruby.ST.latency_hist_seqr::samples 46 | 906system.ruby.ST.latency_hist_seqr::bucket_size 1024 907system.ruby.ST.latency_hist_seqr::max_bucket 10239 908system.ruby.ST.latency_hist_seqr::samples 46 |
| 906system.ruby.ST.latency_hist_seqr::mean 3269.239130 907system.ruby.ST.latency_hist_seqr::gmean 1783.447677 908system.ruby.ST.latency_hist_seqr::stdev 1934.416354 909system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 18 39.13% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 909system.ruby.ST.latency_hist_seqr::mean 3234.260870 910system.ruby.ST.latency_hist_seqr::gmean 1760.149244 911system.ruby.ST.latency_hist_seqr::stdev 1907.255858 912system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 20 43.48% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 910system.ruby.ST.latency_hist_seqr::total 46 911system.ruby.ST.latency_hist_coalsr::bucket_size 128 912system.ruby.ST.latency_hist_coalsr::max_bucket 1279 | 913system.ruby.ST.latency_hist_seqr::total 46 914system.ruby.ST.latency_hist_coalsr::bucket_size 128 915system.ruby.ST.latency_hist_coalsr::max_bucket 1279 |
| 913system.ruby.ST.latency_hist_coalsr::samples 803 914system.ruby.ST.latency_hist_coalsr::mean 231.610212 915system.ruby.ST.latency_hist_coalsr::gmean 117.827816 916system.ruby.ST.latency_hist_coalsr::stdev 248.057845 917system.ruby.ST.latency_hist_coalsr | 517 64.38% 64.38% | 28 3.49% 67.87% | 108 13.45% 81.32% | 38 4.73% 86.05% | 33 4.11% 90.16% | 19 2.37% 92.53% | 33 4.11% 96.64% | 23 2.86% 99.50% | 4 0.50% 100.00% | 0 0.00% 100.00% 918system.ruby.ST.latency_hist_coalsr::total 803 | 916system.ruby.ST.latency_hist_coalsr::samples 786 917system.ruby.ST.latency_hist_coalsr::mean 225.797710 918system.ruby.ST.latency_hist_coalsr::gmean 112.544056 919system.ruby.ST.latency_hist_coalsr::stdev 244.652456 920system.ruby.ST.latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00% 921system.ruby.ST.latency_hist_coalsr::total 786 |
| 919system.ruby.ST.hit_latency_hist_seqr::bucket_size 1024 920system.ruby.ST.hit_latency_hist_seqr::max_bucket 10239 921system.ruby.ST.hit_latency_hist_seqr::samples 40 | 922system.ruby.ST.hit_latency_hist_seqr::bucket_size 1024 923system.ruby.ST.hit_latency_hist_seqr::max_bucket 10239 924system.ruby.ST.hit_latency_hist_seqr::samples 40 |
| 922system.ruby.ST.hit_latency_hist_seqr::mean 3606.650000 923system.ruby.ST.hit_latency_hist_seqr::gmean 2691.718970 924system.ruby.ST.hit_latency_hist_seqr::stdev 1792.166924 925system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 925system.ruby.ST.hit_latency_hist_seqr::mean 3566.725000 926system.ruby.ST.hit_latency_hist_seqr::gmean 2651.630943 927system.ruby.ST.hit_latency_hist_seqr::stdev 1765.919997 928system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 926system.ruby.ST.hit_latency_hist_seqr::total 40 927system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 928system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 929system.ruby.ST.miss_latency_hist_seqr::samples 6 | 929system.ruby.ST.hit_latency_hist_seqr::total 40 930system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 931system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 932system.ruby.ST.miss_latency_hist_seqr::samples 6 |
| 930system.ruby.ST.miss_latency_hist_seqr::mean 1019.833333 931system.ruby.ST.miss_latency_hist_seqr::gmean 114.673945 932system.ruby.ST.miss_latency_hist_seqr::stdev 1281.644790 933system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 933system.ruby.ST.miss_latency_hist_seqr::mean 1017.833333 934system.ruby.ST.miss_latency_hist_seqr::gmean 114.584426 935system.ruby.ST.miss_latency_hist_seqr::stdev 1278.753677 936system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 934system.ruby.ST.miss_latency_hist_seqr::total 6 935system.ruby.ST.miss_latency_hist_coalsr::bucket_size 128 936system.ruby.ST.miss_latency_hist_coalsr::max_bucket 1279 | 937system.ruby.ST.miss_latency_hist_seqr::total 6 938system.ruby.ST.miss_latency_hist_coalsr::bucket_size 128 939system.ruby.ST.miss_latency_hist_coalsr::max_bucket 1279 |
| 937system.ruby.ST.miss_latency_hist_coalsr::samples 803 938system.ruby.ST.miss_latency_hist_coalsr::mean 231.610212 939system.ruby.ST.miss_latency_hist_coalsr::gmean 117.827816 940system.ruby.ST.miss_latency_hist_coalsr::stdev 248.057845 941system.ruby.ST.miss_latency_hist_coalsr | 517 64.38% 64.38% | 28 3.49% 67.87% | 108 13.45% 81.32% | 38 4.73% 86.05% | 33 4.11% 90.16% | 19 2.37% 92.53% | 33 4.11% 96.64% | 23 2.86% 99.50% | 4 0.50% 100.00% | 0 0.00% 100.00% 942system.ruby.ST.miss_latency_hist_coalsr::total 803 | 940system.ruby.ST.miss_latency_hist_coalsr::samples 786 941system.ruby.ST.miss_latency_hist_coalsr::mean 225.797710 942system.ruby.ST.miss_latency_hist_coalsr::gmean 112.544056 943system.ruby.ST.miss_latency_hist_coalsr::stdev 244.652456 944system.ruby.ST.miss_latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00% 945system.ruby.ST.miss_latency_hist_coalsr::total 786 |
| 943system.ruby.IFETCH.latency_hist_seqr::bucket_size 1024 944system.ruby.IFETCH.latency_hist_seqr::max_bucket 10239 945system.ruby.IFETCH.latency_hist_seqr::samples 1 | 946system.ruby.IFETCH.latency_hist_seqr::bucket_size 1024 947system.ruby.IFETCH.latency_hist_seqr::max_bucket 10239 948system.ruby.IFETCH.latency_hist_seqr::samples 1 |
| 946system.ruby.IFETCH.latency_hist_seqr::mean 5156 947system.ruby.IFETCH.latency_hist_seqr::gmean 5156.000000 | 949system.ruby.IFETCH.latency_hist_seqr::mean 5129 950system.ruby.IFETCH.latency_hist_seqr::gmean 5129 |
| 948system.ruby.IFETCH.latency_hist_seqr::stdev nan 949system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 950system.ruby.IFETCH.latency_hist_seqr::total 1 951system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1024 952system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 10239 953system.ruby.IFETCH.hit_latency_hist_seqr::samples 1 | 951system.ruby.IFETCH.latency_hist_seqr::stdev nan 952system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 953system.ruby.IFETCH.latency_hist_seqr::total 1 954system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1024 955system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 10239 956system.ruby.IFETCH.hit_latency_hist_seqr::samples 1 |
| 954system.ruby.IFETCH.hit_latency_hist_seqr::mean 5156 955system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5156.000000 | 957system.ruby.IFETCH.hit_latency_hist_seqr::mean 5129 958system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5129 |
| 956system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan 957system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 958system.ruby.IFETCH.hit_latency_hist_seqr::total 1 959system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 960system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 961system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 6 | 959system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan 960system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 961system.ruby.IFETCH.hit_latency_hist_seqr::total 1 962system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 963system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 964system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 6 |
| 962system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1019.833333 963system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.673945 964system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1281.644790 965system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 965system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1017.833333 966system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.584426 967system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1278.753677 968system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 966system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 6 967system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 1024 968system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 10239 969system.ruby.Directory.hit_mach_latency_hist_seqr::samples 42 | 969system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 6 970system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 1024 971system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 10239 972system.ruby.Directory.hit_mach_latency_hist_seqr::samples 42 |
| 970system.ruby.Directory.hit_mach_latency_hist_seqr::mean 3684.428571 971system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2778.454716 972system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1783.107224 973system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 973system.ruby.Directory.hit_mach_latency_hist_seqr::mean 3644.142857 974system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2737.850881 975system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1757.652877 976system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 974system.ruby.Directory.hit_mach_latency_hist_seqr::total 42 975system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 128 976system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 1279 | 977system.ruby.Directory.hit_mach_latency_hist_seqr::total 42 978system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 128 979system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 1279 |
| 977system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 644 978system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 154.992236 979system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 124.686138 980system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 142.628867 981system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 516 80.12% 80.12% | 30 4.66% 84.78% | 42 6.52% 91.30% | 26 4.04% 95.34% | 17 2.64% 97.98% | 7 1.09% 99.07% | 4 0.62% 99.69% | 1 0.16% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% 982system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 644 | 980system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 624 981system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 148.483974 982system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 122.381501 983system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 128.958613 984system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 502 80.45% 80.45% | 36 5.77% 86.22% | 40 6.41% 92.63% | 24 3.85% 96.47% | 12 1.92% 98.40% | 6 0.96% 99.36% | 3 0.48% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 985system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 624 |
| 983system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 984system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 | 986system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 987system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 |
| 985system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 64 986system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.109375 987system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.055645 988system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.537991 989system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 61 95.31% 95.31% | 1 1.56% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 990system.ruby.TCP.miss_mach_latency_hist_coalsr::total 64 | 988system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 71 989system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.126761 990system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.060325 991system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.607796 992system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 68 95.77% 95.77% | 0 0.00% 95.77% | 0 0.00% 95.77% | 3 4.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 993system.ruby.TCP.miss_mach_latency_hist_coalsr::total 71 |
| 991system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 128 992system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279 | 994system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 128 995system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279 |
| 993system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 164 994system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 571.804878 995system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 508.667381 996system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 267.247131 997system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 41.46% 41.46% | 13 7.93% 49.39% | 16 9.76% 59.15% | 13 7.93% 67.07% | 29 17.68% 84.76% | 22 13.41% 98.17% | 3 1.83% 100.00% | 0 0.00% 100.00% 998system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 164 | 996system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 163 997system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 564.687117 998system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 498.870659 999system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 272.472640 1000system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 43.56% 43.56% | 13 7.98% 51.53% | 12 7.36% 58.90% | 13 7.98% 66.87% | 29 17.79% 84.66% | 22 13.50% 98.16% | 3 1.84% 100.00% | 0 0.00% 100.00% 1001system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 163 |
| 999system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 1000system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 1001system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1 | 1002system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 1003system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 1004system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1 |
| 1002system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5324 1003system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5324.000000 | 1005system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5256 1006system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5256.000000 |
| 1004system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan 1005system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1006system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 1 | 1007system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan 1008system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1009system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 1 |
| 1007system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 1008system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 | 1010system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 1011system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 |
| 1009system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62 | 1012system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62 |
| 1010system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 107.322581 1011system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 101.146340 1012system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 70.212972 1013system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 59 95.16% 95.16% | 2 3.23% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1013system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 104.322581 1014system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 100.218451 1015system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 51.260433 1016system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 60 96.77% 96.77% | 1 1.61% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 1014system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62 1015system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 1016system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 | 1017system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62 1018system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 1019system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 |
| 1017system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 4 1018system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1 1019system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 1020system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1021system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 4 1022system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 1023system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 | 1020system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 7 1021system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1.428571 1022system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.219014 1023system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.133893 1024system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 6 85.71% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1025system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 7 1026system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 1027system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 |
| 1024system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3 | 1028system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3 |
| 1025system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 340.333333 1026system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 328.169813 1027system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 116.791838 1028system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1029system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 274.333333 1030system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273.844265 1031system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 20.256686 1032system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% |
| 1029system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3 1030system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 1031system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 1032system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6 | 1033system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3 1034system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 1035system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 1036system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6 |
| 1033system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1019.833333 1034system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.673945 1035system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1281.644790 1036system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1037system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1017.833333 1038system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.584426 1039system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1278.753677 1040system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 1037system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6 1038system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 1039system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 1040system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40 | 1041system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6 1042system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 1043system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 1044system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40 |
| 1041system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3606.650000 1042system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2691.718970 1043system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1792.166924 1044system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1045system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3566.725000 1046system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2651.630943 1047system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1765.919997 1048system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 1045system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40 1046system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 1047system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 | 1049system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40 1050system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 1051system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 |
| 1048system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 582 1049system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 160.070447 1050system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 127.496503 1051system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 147.403962 1052system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 457 78.52% 78.52% | 28 4.81% 83.33% | 42 7.22% 90.55% | 26 4.47% 95.02% | 17 2.92% 97.94% | 6 1.03% 98.97% | 4 0.69% 99.66% | 1 0.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% 1053system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 582 | 1052system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 562 1053system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 153.355872 1054system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 125.108856 1055system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 133.952348 1056system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 442 78.65% 78.65% | 35 6.23% 84.88% | 40 7.12% 91.99% | 23 4.09% 96.09% | 12 2.14% 98.22% | 6 1.07% 99.29% | 3 0.53% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1057system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 562 |
| 1054system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 1055system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 | 1058system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 1059system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 |
| 1056system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 60 1057system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.116667 1058system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.059463 1059system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.555151 1060system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 57 95.00% 95.00% | 1 1.67% 96.67% | 0 0.00% 96.67% | 2 3.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1061system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 60 | 1060system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 64 1061system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.093750 1062system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.044274 1063system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.526104 1064system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 62 96.88% 96.88% | 0 0.00% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1065system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 64 |
| 1062system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128 1063system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279 | 1066system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128 1067system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279 |
| 1064system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 161 1065system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 576.118012 1066system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 512.838367 1067system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 267.518863 1068system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 66 40.99% 40.99% | 12 7.45% 48.45% | 16 9.94% 58.39% | 13 8.07% 66.46% | 29 18.01% 84.47% | 22 13.66% 98.14% | 3 1.86% 100.00% | 0 0.00% 100.00% 1069system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 161 | 1068system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 160 1069system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 570.131250 1070system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 504.512629 1071system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 272.059675 1072system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 42.50% 42.50% | 13 8.12% 50.62% | 12 7.50% 58.12% | 13 8.12% 66.25% | 29 18.12% 84.38% | 22 13.75% 98.12% | 3 1.88% 100.00% | 0 0.00% 100.00% 1073system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 160 |
| 1070system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 1071system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 1072system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1 | 1074system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 1075system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 1076system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1 |
| 1073system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5156 1074system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5156.000000 | 1077system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5129 1078system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5129 |
| 1075system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan 1076system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1077system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1 | 1079system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan 1080system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1081system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1 |
| 1078system.ruby.SQC_Controller.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% 1079system.ruby.SQC_Controller.Fetch::total 27 1080system.ruby.SQC_Controller.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% 1081system.ruby.SQC_Controller.TCC_AckS::total 27 1082system.ruby.SQC_Controller.PrbInvData | 10 41.67% 41.67% | 14 58.33% 100.00% 1083system.ruby.SQC_Controller.PrbInvData::total 24 1084system.ruby.SQC_Controller.I.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% 1085system.ruby.SQC_Controller.I.Fetch::total 27 1086system.ruby.SQC_Controller.S.PrbInvData | 10 41.67% 41.67% | 14 58.33% 100.00% 1087system.ruby.SQC_Controller.S.PrbInvData::total 24 1088system.ruby.SQC_Controller.I_S.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% 1089system.ruby.SQC_Controller.I_S.TCC_AckS::total 27 1090system.ruby.TCCdir_Controller.RdBlk 174 0.00% 0.00% 1091system.ruby.TCCdir_Controller.RdBlkM 2638 0.00% 0.00% 1092system.ruby.TCCdir_Controller.RdBlkS 195 0.00% 0.00% 1093system.ruby.TCCdir_Controller.CPUPrbResp 811 0.00% 0.00% 1094system.ruby.TCCdir_Controller.ProbeAcksComplete 751 0.00% 0.00% 1095system.ruby.TCCdir_Controller.CoreUnblock 829 0.00% 0.00% 1096system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% 1097system.ruby.TCCdir_Controller.NB_AckS 2 0.00% 0.00% 1098system.ruby.TCCdir_Controller.NB_AckE 2 0.00% 0.00% 1099system.ruby.TCCdir_Controller.NB_AckM 223 0.00% 0.00% 1100system.ruby.TCCdir_Controller.PrbInvData 112 0.00% 0.00% 1101system.ruby.TCCdir_Controller.PrbShrData 4 0.00% 0.00% | 1082system.ruby.SQC_Controller.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00% 1083system.ruby.SQC_Controller.Fetch::total 24 1084system.ruby.SQC_Controller.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00% 1085system.ruby.SQC_Controller.TCC_AckS::total 24 1086system.ruby.SQC_Controller.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00% 1087system.ruby.SQC_Controller.PrbInvData::total 22 1088system.ruby.SQC_Controller.I.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00% 1089system.ruby.SQC_Controller.I.Fetch::total 24 1090system.ruby.SQC_Controller.S.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00% 1091system.ruby.SQC_Controller.S.PrbInvData::total 22 1092system.ruby.SQC_Controller.I_S.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00% 1093system.ruby.SQC_Controller.I_S.TCC_AckS::total 24 1094system.ruby.TCCdir_Controller.RdBlk 115 0.00% 0.00% 1095system.ruby.TCCdir_Controller.RdBlkM 2448 0.00% 0.00% 1096system.ruby.TCCdir_Controller.RdBlkS 103 0.00% 0.00% 1097system.ruby.TCCdir_Controller.CPUPrbResp 785 0.00% 0.00% 1098system.ruby.TCCdir_Controller.ProbeAcksComplete 730 0.00% 0.00% 1099system.ruby.TCCdir_Controller.CoreUnblock 807 0.00% 0.00% 1100system.ruby.TCCdir_Controller.LastCoreUnblock 3 0.00% 0.00% 1101system.ruby.TCCdir_Controller.NB_AckS 1 0.00% 0.00% 1102system.ruby.TCCdir_Controller.NB_AckE 3 0.00% 0.00% 1103system.ruby.TCCdir_Controller.NB_AckM 212 0.00% 0.00% 1104system.ruby.TCCdir_Controller.PrbInvData 119 0.00% 0.00% 1105system.ruby.TCCdir_Controller.PrbShrData 6 0.00% 0.00% |
| 1102system.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00% | 1106system.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00% |
| 1103system.ruby.TCCdir_Controller.I.RdBlkM 156 0.00% 0.00% | 1107system.ruby.TCCdir_Controller.I.RdBlkM 154 0.00% 0.00% |
| 1104system.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00% 1105system.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00% | 1108system.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00% 1109system.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00% |
| 1106system.ruby.TCCdir_Controller.S.RdBlkM 2 0.00% 0.00% 1107system.ruby.TCCdir_Controller.S.RdBlkS 1 0.00% 0.00% | 1110system.ruby.TCCdir_Controller.S.RdBlkM 1 0.00% 0.00% |
| 1108system.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00% | 1111system.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00% |
| 1109system.ruby.TCCdir_Controller.O.RdBlk 1 0.00% 0.00% 1110system.ruby.TCCdir_Controller.O.RdBlkM 70 0.00% 0.00% 1111system.ruby.TCCdir_Controller.O.PrbInvData 6 0.00% 0.00% | 1112system.ruby.TCCdir_Controller.E.RdBlkS 1 0.00% 0.00% 1113system.ruby.TCCdir_Controller.O.RdBlk 2 0.00% 0.00% 1114system.ruby.TCCdir_Controller.O.RdBlkM 61 0.00% 0.00% 1115system.ruby.TCCdir_Controller.O.RdBlkS 1 0.00% 0.00% 1116system.ruby.TCCdir_Controller.O.PrbInvData 4 0.00% 0.00% 1117system.ruby.TCCdir_Controller.O.PrbShrData 1 0.00% 0.00% |
| 1112system.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00% | 1118system.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00% |
| 1113system.ruby.TCCdir_Controller.M.RdBlkM 521 0.00% 0.00% 1114system.ruby.TCCdir_Controller.M.RdBlkS 25 0.00% 0.00% 1115system.ruby.TCCdir_Controller.M.PrbInvData 59 0.00% 0.00% | 1119system.ruby.TCCdir_Controller.M.RdBlkM 512 0.00% 0.00% 1120system.ruby.TCCdir_Controller.M.RdBlkS 20 0.00% 0.00% 1121system.ruby.TCCdir_Controller.M.PrbInvData 62 0.00% 0.00% |
| 1116system.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00% | 1122system.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00% |
| 1117system.ruby.TCCdir_Controller.CP_I.RdBlk 9 0.00% 0.00% 1118system.ruby.TCCdir_Controller.CP_I.RdBlkM 15 0.00% 0.00% 1119system.ruby.TCCdir_Controller.CP_I.RdBlkS 7 0.00% 0.00% 1120system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 71 0.00% 0.00% 1121system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 65 0.00% 0.00% | 1123system.ruby.TCCdir_Controller.CP_I.RdBlkM 17 0.00% 0.00% 1124system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 70 0.00% 0.00% 1125system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 66 0.00% 0.00% |
| 1122system.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00% | 1126system.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00% |
| 1123system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 4 0.00% 0.00% 1124system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 4 0.00% 0.00% | 1127system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 6 0.00% 0.00% 1128system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 5 0.00% 0.00% 1129system.ruby.TCCdir_Controller.CP_OM.RdBlkM 14 0.00% 0.00% 1130system.ruby.TCCdir_Controller.CP_OM.CPUPrbResp 1 0.00% 0.00% 1131system.ruby.TCCdir_Controller.CP_OM.ProbeAcksComplete 1 0.00% 0.00% |
| 1125system.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00% 1126system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00% 1127system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00% | 1132system.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00% 1133system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00% 1134system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00% |
| 1128system.ruby.TCCdir_Controller.I_M.RdBlkM 897 0.00% 0.00% 1129system.ruby.TCCdir_Controller.I_M.RdBlkS 30 0.00% 0.00% 1130system.ruby.TCCdir_Controller.I_M.NB_AckM 156 0.00% 0.00% | 1135system.ruby.TCCdir_Controller.I_M.RdBlk 26 0.00% 0.00% 1136system.ruby.TCCdir_Controller.I_M.RdBlkM 960 0.00% 0.00% 1137system.ruby.TCCdir_Controller.I_M.RdBlkS 3 0.00% 0.00% 1138system.ruby.TCCdir_Controller.I_M.NB_AckM 154 0.00% 0.00% |
| 1131system.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00% | 1139system.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00% |
| 1132system.ruby.TCCdir_Controller.I_ES.RdBlkM 24 0.00% 0.00% 1133system.ruby.TCCdir_Controller.I_ES.RdBlkS 34 0.00% 0.00% 1134system.ruby.TCCdir_Controller.I_ES.NB_AckS 1 0.00% 0.00% 1135system.ruby.TCCdir_Controller.I_ES.NB_AckE 2 0.00% 0.00% 1136system.ruby.TCCdir_Controller.I_S.RdBlkM 11 0.00% 0.00% | 1140system.ruby.TCCdir_Controller.I_ES.NB_AckE 3 0.00% 0.00% |
| 1137system.ruby.TCCdir_Controller.I_S.NB_AckS 1 0.00% 0.00% | 1141system.ruby.TCCdir_Controller.I_S.NB_AckS 1 0.00% 0.00% |
| 1138system.ruby.TCCdir_Controller.BBS_S.RdBlkM 5 0.00% 0.00% 1139system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 1 0.00% 0.00% 1140system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 1 0.00% 0.00% 1141system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 1 0.00% 0.00% 1142system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 1 0.00% 0.00% 1143system.ruby.TCCdir_Controller.BBM_M.RdBlk 11 0.00% 0.00% 1144system.ruby.TCCdir_Controller.BBM_M.RdBlkM 104 0.00% 0.00% 1145system.ruby.TCCdir_Controller.BBM_M.RdBlkS 12 0.00% 0.00% 1146system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 520 0.00% 0.00% 1147system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 520 0.00% 0.00% 1148system.ruby.TCCdir_Controller.BBM_M.PrbInvData 14 0.00% 0.00% 1149system.ruby.TCCdir_Controller.BBM_O.RdBlkM 13 0.00% 0.00% 1150system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 86 0.00% 0.00% 1151system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 86 0.00% 0.00% 1152system.ruby.TCCdir_Controller.BB_M.RdBlk 20 0.00% 0.00% 1153system.ruby.TCCdir_Controller.BB_M.RdBlkM 181 0.00% 0.00% 1154system.ruby.TCCdir_Controller.BB_M.RdBlkS 15 0.00% 0.00% 1155system.ruby.TCCdir_Controller.BB_M.CoreUnblock 518 0.00% 0.00% 1156system.ruby.TCCdir_Controller.BB_M.PrbInvData 19 0.00% 0.00% 1157system.ruby.TCCdir_Controller.BB_O.RdBlkM 35 0.00% 0.00% 1158system.ruby.TCCdir_Controller.BB_O.CoreUnblock 84 0.00% 0.00% | 1142system.ruby.TCCdir_Controller.BBO_O.RdBlkM 5 0.00% 0.00% 1143system.ruby.TCCdir_Controller.BBO_O.RdBlkS 1 0.00% 0.00% 1144system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 3 0.00% 0.00% 1145system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 3 0.00% 0.00% 1146system.ruby.TCCdir_Controller.BBM_M.RdBlk 6 0.00% 0.00% 1147system.ruby.TCCdir_Controller.BBM_M.RdBlkM 94 0.00% 0.00% 1148system.ruby.TCCdir_Controller.BBM_M.RdBlkS 5 0.00% 0.00% 1149system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 510 0.00% 0.00% 1150system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 510 0.00% 0.00% 1151system.ruby.TCCdir_Controller.BBM_M.PrbInvData 15 0.00% 0.00% 1152system.ruby.TCCdir_Controller.BBM_O.RdBlkM 6 0.00% 0.00% 1153system.ruby.TCCdir_Controller.BBM_O.RdBlkS 5 0.00% 0.00% 1154system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 81 0.00% 0.00% 1155system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 81 0.00% 0.00% 1156system.ruby.TCCdir_Controller.BB_M.RdBlk 13 0.00% 0.00% 1157system.ruby.TCCdir_Controller.BB_M.RdBlkM 176 0.00% 0.00% 1158system.ruby.TCCdir_Controller.BB_M.RdBlkS 5 0.00% 0.00% 1159system.ruby.TCCdir_Controller.BB_M.CoreUnblock 509 0.00% 0.00% 1160system.ruby.TCCdir_Controller.BB_M.PrbInvData 24 0.00% 0.00% 1161system.ruby.TCCdir_Controller.BB_O.RdBlkM 26 0.00% 0.00% 1162system.ruby.TCCdir_Controller.BB_O.RdBlkS 5 0.00% 0.00% 1163system.ruby.TCCdir_Controller.BB_O.CoreUnblock 81 0.00% 0.00% |
| 1159system.ruby.TCCdir_Controller.BB_O.PrbInvData 2 0.00% 0.00% | 1164system.ruby.TCCdir_Controller.BB_O.PrbInvData 2 0.00% 0.00% |
| 1160system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 1 0.00% 0.00% 1161system.ruby.TCCdir_Controller.BB_S.RdBlkM 9 0.00% 0.00% 1162system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 1 0.00% 0.00% 1163system.ruby.TCCdir_Controller.BBS_M.RdBlk 9 0.00% 0.00% 1164system.ruby.TCCdir_Controller.BBS_M.RdBlkM 18 0.00% 0.00% 1165system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 4 0.00% 0.00% 1166system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 3 0.00% 0.00% 1167system.ruby.TCCdir_Controller.BBO_M.RdBlkM 20 0.00% 0.00% 1168system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 122 0.00% 0.00% 1169system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 69 0.00% 0.00% 1170system.ruby.TCCdir_Controller.S_M.RdBlk 28 0.00% 0.00% 1171system.ruby.TCCdir_Controller.S_M.RdBlkM 69 0.00% 0.00% 1172system.ruby.TCCdir_Controller.S_M.NB_AckM 3 0.00% 0.00% 1173system.ruby.TCCdir_Controller.O_M.RdBlk 20 0.00% 0.00% 1174system.ruby.TCCdir_Controller.O_M.RdBlkM 249 0.00% 0.00% 1175system.ruby.TCCdir_Controller.O_M.RdBlkS 51 0.00% 0.00% 1176system.ruby.TCCdir_Controller.O_M.NB_AckM 64 0.00% 0.00% | 1165system.ruby.TCCdir_Controller.BB_OO.RdBlkM 14 0.00% 0.00% 1166system.ruby.TCCdir_Controller.BB_OO.CoreUnblock 1 0.00% 0.00% 1167system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 3 0.00% 0.00% 1168system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 2 0.00% 0.00% 1169system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 2 0.00% 0.00% 1170system.ruby.TCCdir_Controller.BBO_M.RdBlkM 4 0.00% 0.00% 1171system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 110 0.00% 0.00% 1172system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 60 0.00% 0.00% 1173system.ruby.TCCdir_Controller.S_M.NB_AckM 2 0.00% 0.00% 1174system.ruby.TCCdir_Controller.O_M.RdBlkM 198 0.00% 0.00% 1175system.ruby.TCCdir_Controller.O_M.RdBlkS 48 0.00% 0.00% 1176system.ruby.TCCdir_Controller.O_M.NB_AckM 56 0.00% 0.00% |
| 1177system.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00% | 1177system.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00% |
| 1178system.ruby.TCCdir_Controller.BBB_S.RdBlk 3 0.00% 0.00% 1179system.ruby.TCCdir_Controller.BBB_S.RdBlkM 23 0.00% 0.00% 1180system.ruby.TCCdir_Controller.BBB_S.RdBlkS 5 0.00% 0.00% 1181system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 2 0.00% 0.00% 1182system.ruby.TCCdir_Controller.BBB_M.RdBlk 9 0.00% 0.00% 1183system.ruby.TCCdir_Controller.BBB_M.RdBlkM 206 0.00% 0.00% 1184system.ruby.TCCdir_Controller.BBB_M.RdBlkS 14 0.00% 0.00% 1185system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 223 0.00% 0.00% 1186system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 2 0.00% 0.00% 1187system.ruby.TCP_Controller.Load | 5 7.04% 7.04% | 6 8.45% 15.49% | 10 14.08% 29.58% | 13 18.31% 47.89% | 6 8.45% 56.34% | 6 8.45% 64.79% | 13 18.31% 83.10% | 12 16.90% 100.00% 1188system.ruby.TCP_Controller.Load::total 71 1189system.ruby.TCP_Controller.Store | 109 13.39% 13.39% | 104 12.78% 26.17% | 98 12.04% 38.21% | 93 11.43% 49.63% | 109 13.39% 63.02% | 102 12.53% 75.55% | 113 13.88% 89.43% | 86 10.57% 100.00% 1190system.ruby.TCP_Controller.Store::total 814 1191system.ruby.TCP_Controller.TCC_AckS | 5 7.94% 7.94% | 5 7.94% 15.87% | 9 14.29% 30.16% | 13 20.63% 50.79% | 4 6.35% 57.14% | 6 9.52% 66.67% | 11 17.46% 84.13% | 10 15.87% 100.00% 1192system.ruby.TCP_Controller.TCC_AckS::total 63 1193system.ruby.TCP_Controller.TCC_AckE | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% 1194system.ruby.TCP_Controller.TCC_AckE::total 2 1195system.ruby.TCP_Controller.TCC_AckM | 100 13.46% 13.46% | 94 12.65% 26.11% | 90 12.11% 38.22% | 81 10.90% 49.13% | 102 13.73% 62.85% | 92 12.38% 75.24% | 105 14.13% 89.37% | 79 10.63% 100.00% 1196system.ruby.TCP_Controller.TCC_AckM::total 743 1197system.ruby.TCP_Controller.PrbInvData | 88 12.61% 12.61% | 87 12.46% 25.07% | 88 12.61% 37.68% | 79 11.32% 49.00% | 90 12.89% 61.89% | 86 12.32% 74.21% | 101 14.47% 88.68% | 79 11.32% 100.00% 1198system.ruby.TCP_Controller.PrbInvData::total 698 1199system.ruby.TCP_Controller.PrbShrData | 14 15.22% 15.22% | 9 9.78% 25.00% | 17 18.48% 43.48% | 7 7.61% 51.09% | 14 15.22% 66.30% | 10 10.87% 77.17% | 12 13.04% 90.22% | 9 9.78% 100.00% | 1178system.ruby.TCCdir_Controller.O_M.PrbShrData 1 0.00% 0.00% 1179system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 1 0.00% 0.00% 1180system.ruby.TCCdir_Controller.BBB_M.RdBlk 4 0.00% 0.00% 1181system.ruby.TCCdir_Controller.BBB_M.RdBlkM 196 0.00% 0.00% 1182system.ruby.TCCdir_Controller.BBB_M.RdBlkS 8 0.00% 0.00% 1183system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 212 0.00% 0.00% 1184system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 3 0.00% 0.00% 1185system.ruby.TCP_Controller.Load | 10 13.70% 13.70% | 10 13.70% 27.40% | 11 15.07% 42.47% | 12 16.44% 58.90% | 6 8.22% 67.12% | 3 4.11% 71.23% | 10 13.70% 84.93% | 11 15.07% 100.00% 1186system.ruby.TCP_Controller.Load::total 73 1187system.ruby.TCP_Controller.Store | 106 13.27% 13.27% | 102 12.77% 26.03% | 97 12.14% 38.17% | 86 10.76% 48.94% | 107 13.39% 62.33% | 98 12.27% 74.59% | 111 13.89% 88.49% | 92 11.51% 100.00% 1188system.ruby.TCP_Controller.Store::total 799 1189system.ruby.TCP_Controller.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00% 1190system.ruby.TCP_Controller.TCC_AckS::total 62 1191system.ruby.TCP_Controller.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% 1192system.ruby.TCP_Controller.TCC_AckE::total 3 1193system.ruby.TCP_Controller.TCC_AckM | 93 12.88% 12.88% | 89 12.33% 25.21% | 87 12.05% 37.26% | 76 10.53% 47.78% | 98 13.57% 61.36% | 89 12.33% 73.68% | 106 14.68% 88.37% | 84 11.63% 100.00% 1194system.ruby.TCP_Controller.TCC_AckM::total 722 1195system.ruby.TCP_Controller.PrbInvData | 84 12.44% 12.44% | 87 12.89% 25.33% | 83 12.30% 37.63% | 78 11.56% 49.19% | 89 13.19% 62.37% | 79 11.70% 74.07% | 97 14.37% 88.44% | 78 11.56% 100.00% 1196system.ruby.TCP_Controller.PrbInvData::total 675 1197system.ruby.TCP_Controller.PrbShrData | 16 17.39% 17.39% | 10 10.87% 28.26% | 9 9.78% 38.04% | 8 8.70% 46.74% | 15 16.30% 63.04% | 9 9.78% 72.83% | 14 15.22% 88.04% | 11 11.96% 100.00% |
| 1200system.ruby.TCP_Controller.PrbShrData::total 92 | 1198system.ruby.TCP_Controller.PrbShrData::total 92 |
| 1201system.ruby.TCP_Controller.I.Load | 5 7.46% 7.46% | 5 7.46% 14.93% | 9 13.43% 28.36% | 13 19.40% 47.76% | 6 8.96% 56.72% | 6 8.96% 65.67% | 12 17.91% 83.58% | 11 16.42% 100.00% 1202system.ruby.TCP_Controller.I.Load::total 67 1203system.ruby.TCP_Controller.I.Store | 98 13.26% 13.26% | 95 12.86% 26.12% | 89 12.04% 38.16% | 82 11.10% 49.26% | 99 13.40% 62.65% | 93 12.58% 75.24% | 105 14.21% 89.45% | 78 10.55% 100.00% 1204system.ruby.TCP_Controller.I.Store::total 739 | 1199system.ruby.TCP_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 9 13.64% 42.42% | 12 18.18% 60.61% | 5 7.58% 68.18% | 3 4.55% 72.73% | 9 13.64% 86.36% | 9 13.64% 100.00% 1200system.ruby.TCP_Controller.I.Load::total 66 1201system.ruby.TCP_Controller.I.Store | 97 13.42% 13.42% | 91 12.59% 26.00% | 87 12.03% 38.04% | 79 10.93% 48.96% | 92 12.72% 61.69% | 89 12.31% 74.00% | 104 14.38% 88.38% | 84 11.62% 100.00% 1202system.ruby.TCP_Controller.I.Store::total 723 |
| 1205system.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1206system.ruby.TCP_Controller.I.PrbInvData::total 2 | 1203system.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1204system.ruby.TCP_Controller.I.PrbInvData::total 2 |
| 1207system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% 1208system.ruby.TCP_Controller.S.Store::total 5 1209system.ruby.TCP_Controller.S.PrbInvData | 4 8.33% 8.33% | 4 8.33% 16.67% | 8 16.67% 33.33% | 9 18.75% 52.08% | 3 6.25% 58.33% | 4 8.33% 66.67% | 8 16.67% 83.33% | 8 16.67% 100.00% 1210system.ruby.TCP_Controller.S.PrbInvData::total 48 1211system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1205system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% 1206system.ruby.TCP_Controller.S.Store::total 3 1207system.ruby.TCP_Controller.S.PrbInvData | 6 14.29% 14.29% | 7 16.67% 30.95% | 7 16.67% 47.62% | 7 16.67% 64.29% | 2 4.76% 69.05% | 1 2.38% 71.43% | 5 11.90% 83.33% | 7 16.67% 100.00% 1208system.ruby.TCP_Controller.S.PrbInvData::total 42 1209system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 1212system.ruby.TCP_Controller.S.PrbShrData::total 1 1213system.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 1214system.ruby.TCP_Controller.E.PrbInvData::total 1 | 1210system.ruby.TCP_Controller.S.PrbShrData::total 1 1211system.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 1212system.ruby.TCP_Controller.E.PrbInvData::total 1 |
| 1215system.ruby.TCP_Controller.O.Store | 2 20.00% 20.00% | 0 0.00% 20.00% | 2 20.00% 40.00% | 0 0.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% 1216system.ruby.TCP_Controller.O.Store::total 10 1217system.ruby.TCP_Controller.O.PrbInvData | 9 13.64% 13.64% | 7 10.61% 24.24% | 12 18.18% 42.42% | 7 10.61% 53.03% | 10 15.15% 68.18% | 5 7.58% 75.76% | 10 15.15% 90.91% | 6 9.09% 100.00% 1218system.ruby.TCP_Controller.O.PrbInvData::total 66 1219system.ruby.TCP_Controller.O.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1220system.ruby.TCP_Controller.O.PrbShrData::total 1 1221system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% 1222system.ruby.TCP_Controller.M.Load::total 4 1223system.ruby.TCP_Controller.M.Store | 9 15.00% 15.00% | 9 15.00% 30.00% | 7 11.67% 41.67% | 10 16.67% 58.33% | 6 10.00% 68.33% | 8 13.33% 81.67% | 5 8.33% 90.00% | 6 10.00% 100.00% 1224system.ruby.TCP_Controller.M.Store::total 60 1225system.ruby.TCP_Controller.M.PrbInvData | 75 12.93% 12.93% | 76 13.10% 26.03% | 67 11.55% 37.59% | 62 10.69% 48.28% | 76 13.10% 61.38% | 77 13.28% 74.66% | 82 14.14% 88.79% | 65 11.21% 100.00% 1226system.ruby.TCP_Controller.M.PrbInvData::total 580 1227system.ruby.TCP_Controller.M.PrbShrData | 14 15.56% 15.56% | 8 8.89% 24.44% | 16 17.78% 42.22% | 7 7.78% 50.00% | 14 15.56% 65.56% | 10 11.11% 76.67% | 12 13.33% 90.00% | 9 10.00% 100.00% 1228system.ruby.TCP_Controller.M.PrbShrData::total 90 1229system.ruby.TCP_Controller.I_M.TCC_AckM | 98 13.42% 13.42% | 94 12.88% 26.30% | 89 12.19% 38.49% | 80 10.96% 49.45% | 98 13.42% 62.88% | 91 12.47% 75.34% | 103 14.11% 89.45% | 77 10.55% 100.00% 1230system.ruby.TCP_Controller.I_M.TCC_AckM::total 730 1231system.ruby.TCP_Controller.I_ES.TCC_AckS | 5 7.94% 7.94% | 5 7.94% 15.87% | 9 14.29% 30.16% | 13 20.63% 50.79% | 4 6.35% 57.14% | 6 9.52% 66.67% | 11 17.46% 84.13% | 10 15.87% 100.00% 1232system.ruby.TCP_Controller.I_ES.TCC_AckS::total 63 1233system.ruby.TCP_Controller.I_ES.TCC_AckE | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% 1234system.ruby.TCP_Controller.I_ES.TCC_AckE::total 2 1235system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% 1236system.ruby.TCP_Controller.S_M.TCC_AckM::total 4 1237system.ruby.TCP_Controller.O_M.TCC_AckM | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 3 33.33% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% 1238system.ruby.TCP_Controller.O_M.TCC_AckM::total 9 1239system.ruby.TCP_Controller.O_M.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1240system.ruby.TCP_Controller.O_M.PrbInvData::total 1 | 1213system.ruby.TCP_Controller.E.PrbShrData | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1214system.ruby.TCP_Controller.E.PrbShrData::total 1 1215system.ruby.TCP_Controller.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 5 55.56% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% 1216system.ruby.TCP_Controller.O.Store::total 9 1217system.ruby.TCP_Controller.O.PrbInvData | 9 16.07% 16.07% | 7 12.50% 28.57% | 8 14.29% 42.86% | 8 14.29% 57.14% | 7 12.50% 69.64% | 3 5.36% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00% 1218system.ruby.TCP_Controller.O.PrbInvData::total 56 1219system.ruby.TCP_Controller.O.PrbShrData | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% 1220system.ruby.TCP_Controller.O.PrbShrData::total 3 1221system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 14.29% 14.29% | 2 28.57% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% 1222system.ruby.TCP_Controller.M.Load::total 7 1223system.ruby.TCP_Controller.M.Store | 9 14.06% 14.06% | 11 17.19% 31.25% | 9 14.06% 45.31% | 7 10.94% 56.25% | 9 14.06% 70.31% | 8 12.50% 82.81% | 4 6.25% 89.06% | 7 10.94% 100.00% 1224system.ruby.TCP_Controller.M.Store::total 64 1225system.ruby.TCP_Controller.M.PrbInvData | 69 12.02% 12.02% | 73 12.72% 24.74% | 68 11.85% 36.59% | 62 10.80% 47.39% | 79 13.76% 61.15% | 75 13.07% 74.22% | 82 14.29% 88.50% | 66 11.50% 100.00% 1226system.ruby.TCP_Controller.M.PrbInvData::total 574 1227system.ruby.TCP_Controller.M.PrbShrData | 14 16.47% 16.47% | 10 11.76% 28.24% | 9 10.59% 38.82% | 8 9.41% 48.24% | 14 16.47% 64.71% | 6 7.06% 71.76% | 14 16.47% 88.24% | 10 11.76% 100.00% 1228system.ruby.TCP_Controller.M.PrbShrData::total 85 1229system.ruby.TCP_Controller.I_M.TCC_AckM | 93 13.06% 13.06% | 89 12.50% 25.56% | 86 12.08% 37.64% | 76 10.67% 48.31% | 92 12.92% 61.24% | 89 12.50% 73.74% | 104 14.61% 88.34% | 83 11.66% 100.00% 1230system.ruby.TCP_Controller.I_M.TCC_AckM::total 712 1231system.ruby.TCP_Controller.I_ES.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00% 1232system.ruby.TCP_Controller.I_ES.TCC_AckS::total 62 1233system.ruby.TCP_Controller.I_ES.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% 1234system.ruby.TCP_Controller.I_ES.TCC_AckE::total 3 1235system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% 1236system.ruby.TCP_Controller.S_M.TCC_AckM::total 2 1237system.ruby.TCP_Controller.O_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 12.50% 12.50% | 0 0.00% 12.50% | 5 62.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% 1238system.ruby.TCP_Controller.O_M.TCC_AckM::total 8 1239system.ruby.TCP_Controller.O_M.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 1240system.ruby.TCP_Controller.O_M.PrbShrData::total 2 |
| 1241 1242---------- End Simulation Statistics ---------- | 1241 1242---------- End Simulation Statistics ---------- |