| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.203116 # Number of seconds simulated 4sim_ticks 203115946500 # Number of ticks simulated 5final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.203261 # Number of seconds simulated 4sim_ticks 203260902500 # Number of ticks simulated 5final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1206960 # Simulator instruction rate (inst/s) 8host_op_rate 1222588 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1824068108 # Simulator tick rate (ticks/s) 10host_mem_usage 256216 # Number of bytes of host memory used 11host_seconds 111.35 # Real time elapsed on the host | 7host_inst_rate 1624841 # Simulator instruction rate (inst/s) 8host_op_rate 1645879 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2457359114 # Simulator tick rate (ticks/s) 10host_mem_usage 261872 # Number of bytes of host memory used 11host_seconds 82.72 # Real time elapsed on the host |
| 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 526720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7845184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8371904 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 526720 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 526720 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5476224 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5476224 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8230 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 122581 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 130811 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 85566 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 85566 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 2591349 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 38596621 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 41187970 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 2591349 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 2591349 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 26941846 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 26941846 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 26941846 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 2591349 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 38596621 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 68129817 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states |
| 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.workload.num_syscalls 1946 # Number of system calls | 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 43system.cpu.pwrStateResidencyTicks::ON 203115946500 # Cumulative time (in ticks) in various power states 44system.cpu.numCycles 406231893 # number of cpu cycles simulated | 43system.cpu.pwrStateResidencyTicks::ON 203260902500 # Cumulative time (in ticks) in various power states 44system.cpu.numCycles 406521805 # number of cpu cycles simulated |
| 45system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 46system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47system.cpu.committedInsts 134398959 # Number of instructions committed 48system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 49system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 50system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 51system.cpu.num_func_calls 1709332 # number of times a function call or return occured 52system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls 53system.cpu.num_int_insts 115187757 # number of integer instructions 54system.cpu.num_fp_insts 2326976 # number of float instructions 55system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read 56system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written 57system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read 58system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 59system.cpu.num_mem_refs 58160261 # number of memory refs 60system.cpu.num_load_insts 37275864 # Number of load instructions 61system.cpu.num_store_insts 20884397 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 45system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 46system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47system.cpu.committedInsts 134398959 # Number of instructions committed 48system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 49system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 50system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 51system.cpu.num_func_calls 1709332 # number of times a function call or return occured 52system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls 53system.cpu.num_int_insts 115187757 # number of integer instructions 54system.cpu.num_fp_insts 2326976 # number of float instructions 55system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read 56system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written 57system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read 58system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 59system.cpu.num_mem_refs 58160261 # number of memory refs 60system.cpu.num_load_insts 37275864 # Number of load instructions 61system.cpu.num_store_insts 20884397 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 63system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles | 63system.cpu.num_busy_cycles 406521804.998000 # Number of busy cycles |
| 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 12719094 # Number of branches fetched 67system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 68system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction 69system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 97system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction 98system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 136293808 # Class of executed instruction | 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 12719094 # Number of branches fetched 67system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 68system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction 69system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 97system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction 98system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 136293808 # Class of executed instruction |
| 102system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states | 102system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states |
| 103system.cpu.dcache.tags.replacements 146583 # number of replacements | 103system.cpu.dcache.tags.replacements 146583 # number of replacements |
| 104system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use | 104system.cpu.dcache.tags.tagsinuse 4087.215868 # Cycle average of tags in use |
| 105system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 106system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 107system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. | 105system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 106system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 107system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. |
| 108system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. 109system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor 110system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy | 108system.cpu.dcache.tags.warmup_cycle 829975500 # Cycle when the warmup percentage was hit. 109system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868 # Average occupied blocks per requestor 110system.cpu.dcache.tags.occ_percent::cpu.data 0.997855 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_percent::total 0.997855 # Average percentage of cache occupancy |
| 112system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id | 112system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id |
| 114system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id | 114system.cpu.dcache.tags.age_task_id_blocks_1024::1 462 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598 # Occupied blocks per task id |
| 116system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 117system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 118system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses | 116system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 117system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 118system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses |
| 119system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states | 119system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states |
| 120system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 124system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 125system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 126system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 127system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits --- 4 unchanged lines hidden (view full) --- 132system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 133system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 134system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 135system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 136system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses 137system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses 138system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses 139system.cpu.dcache.overall_misses::total 150664 # number of overall misses | 120system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 124system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 125system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 126system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 127system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits --- 4 unchanged lines hidden (view full) --- 132system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 133system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 134system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 135system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 136system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses 137system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses 138system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses 139system.cpu.dcache.overall_misses::total 150664 # number of overall misses |
| 140system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles 141system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles 142system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles 143system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles 144system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles 145system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles 146system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles 147system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles 148system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles 149system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles | 140system.cpu.dcache.ReadReq_miss_latency::cpu.data 1655141000 # number of ReadReq miss cycles 141system.cpu.dcache.ReadReq_miss_latency::total 1655141000 # number of ReadReq miss cycles 142system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433166000 # number of WriteReq miss cycles 143system.cpu.dcache.WriteReq_miss_latency::total 6433166000 # number of WriteReq miss cycles 144system.cpu.dcache.SwapReq_miss_latency::cpu.data 446000 # number of SwapReq miss cycles 145system.cpu.dcache.SwapReq_miss_latency::total 446000 # number of SwapReq miss cycles 146system.cpu.dcache.demand_miss_latency::cpu.data 8088307000 # number of demand (read+write) miss cycles 147system.cpu.dcache.demand_miss_latency::total 8088307000 # number of demand (read+write) miss cycles 148system.cpu.dcache.overall_miss_latency::cpu.data 8088307000 # number of overall miss cycles 149system.cpu.dcache.overall_miss_latency::total 8088307000 # number of overall miss cycles |
| 150system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 151system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 152system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 153system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 154system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 155system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 156system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 157system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 162system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 163system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 164system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 165system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 166system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 167system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 168system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 169system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses | 150system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 151system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 152system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 153system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 154system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 155system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 156system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 157system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 162system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 163system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 164system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 165system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 166system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 167system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 168system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 169system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses |
| 170system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency 171system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency 172system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency 173system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency 174system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency 175system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency 176system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency 177system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency 179system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency | 170system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36376.725275 # average ReadReq miss latency 171system.cpu.dcache.ReadReq_avg_miss_latency::total 36376.725275 # average ReadReq miss latency 172system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61172.701685 # average WriteReq miss latency 173system.cpu.dcache.WriteReq_avg_miss_latency::total 61172.701685 # average WriteReq miss latency 174system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29733.333333 # average SwapReq miss latency 175system.cpu.dcache.SwapReq_avg_miss_latency::total 29733.333333 # average SwapReq miss latency 176system.cpu.dcache.demand_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency 177system.cpu.dcache.demand_avg_miss_latency::total 53684.403706 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency 179system.cpu.dcache.overall_avg_miss_latency::total 53684.403706 # average overall miss latency |
| 180system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 180system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 186system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks 187system.cpu.dcache.writebacks::total 123865 # number of writebacks | 186system.cpu.dcache.writebacks::writebacks 123615 # number of writebacks 187system.cpu.dcache.writebacks::total 123615 # number of writebacks |
| 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 192system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 193system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 194system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses 195system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses 196system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses 197system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses | 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 192system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 193system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 194system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses 195system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses 196system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses 197system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses |
| 198system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles 199system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles 200system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles 201system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles 202system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles 203system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles 204system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles 205system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles 206system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles 207system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles | 198system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1609641000 # number of ReadReq MSHR miss cycles 199system.cpu.dcache.ReadReq_mshr_miss_latency::total 1609641000 # number of ReadReq MSHR miss cycles 200system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6328002000 # number of WriteReq MSHR miss cycles 201system.cpu.dcache.WriteReq_mshr_miss_latency::total 6328002000 # number of WriteReq MSHR miss cycles 202system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 431000 # number of SwapReq MSHR miss cycles 203system.cpu.dcache.SwapReq_mshr_miss_latency::total 431000 # number of SwapReq MSHR miss cycles 204system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7937643000 # number of demand (read+write) MSHR miss cycles 205system.cpu.dcache.demand_mshr_miss_latency::total 7937643000 # number of demand (read+write) MSHR miss cycles 206system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7937643000 # number of overall MSHR miss cycles 207system.cpu.dcache.overall_mshr_miss_latency::total 7937643000 # number of overall MSHR miss cycles |
| 208system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 209system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 210system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 211system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 212system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 213system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 214system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 215system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 216system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 217system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses | 208system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 209system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 210system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 211system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 212system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 213system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 214system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 215system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 216system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 217system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses |
| 218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency 219system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency 220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency 221system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency 222system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency 223system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 228system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states | 218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35376.725275 # average ReadReq mshr miss latency 219system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35376.725275 # average ReadReq mshr miss latency 220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60172.701685 # average WriteReq mshr miss latency 221system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60172.701685 # average WriteReq mshr miss latency 222system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28733.333333 # average SwapReq mshr miss latency 223system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28733.333333 # average SwapReq mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency 228system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states |
| 229system.cpu.icache.tags.replacements 184976 # number of replacements | 229system.cpu.icache.tags.replacements 184976 # number of replacements |
| 230system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use | 230system.cpu.icache.tags.tagsinuse 2004.091327 # Cycle average of tags in use |
| 231system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 232system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 233system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. | 231system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 232system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 233system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. |
| 234system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. 235system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor 236system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy 237system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy | 234system.cpu.icache.tags.warmup_cycle 144688165500 # Cycle when the warmup percentage was hit. 235system.cpu.icache.tags.occ_blocks::cpu.inst 2004.091327 # Average occupied blocks per requestor 236system.cpu.icache.tags.occ_percent::cpu.inst 0.978560 # Average percentage of cache occupancy 237system.cpu.icache.tags.occ_percent::total 0.978560 # Average percentage of cache occupancy |
| 238system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id | 238system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id |
| 239system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id | 239system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id |
| 241system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 242system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 243system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 244system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 245system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 246system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses | 241system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 242system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 243system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 244system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 245system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 246system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses |
| 247system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states | 247system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states |
| 248system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 249system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 250system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 251system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 252system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 253system.cpu.icache.overall_hits::total 134366557 # number of overall hits 254system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 255system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 256system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 257system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 258system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 259system.cpu.icache.overall_misses::total 187024 # number of overall misses | 248system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 249system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 250system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 251system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 252system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 253system.cpu.icache.overall_hits::total 134366557 # number of overall hits 254system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 255system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 256system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 257system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 258system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 259system.cpu.icache.overall_misses::total 187024 # number of overall misses |
| 260system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles 261system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles 262system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles 263system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles 264system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles 265system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles | 260system.cpu.icache.ReadReq_miss_latency::cpu.inst 2844752500 # number of ReadReq miss cycles 261system.cpu.icache.ReadReq_miss_latency::total 2844752500 # number of ReadReq miss cycles 262system.cpu.icache.demand_miss_latency::cpu.inst 2844752500 # number of demand (read+write) miss cycles 263system.cpu.icache.demand_miss_latency::total 2844752500 # number of demand (read+write) miss cycles 264system.cpu.icache.overall_miss_latency::cpu.inst 2844752500 # number of overall miss cycles 265system.cpu.icache.overall_miss_latency::total 2844752500 # number of overall miss cycles |
| 266system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) 267system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) 268system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses 269system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses 270system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses 271system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses 272system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 273system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 274system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 275system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 276system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 277system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses | 266system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) 267system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) 268system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses 269system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses 270system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses 271system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses 272system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 273system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 274system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 275system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 276system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 277system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses |
| 278system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency 279system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency 280system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency 281system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency 282system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency 283system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency | 278system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15210.628048 # average ReadReq miss latency 279system.cpu.icache.ReadReq_avg_miss_latency::total 15210.628048 # average ReadReq miss latency 280system.cpu.icache.demand_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency 281system.cpu.icache.demand_avg_miss_latency::total 15210.628048 # average overall miss latency 282system.cpu.icache.overall_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency 283system.cpu.icache.overall_avg_miss_latency::total 15210.628048 # average overall miss latency |
| 284system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 285system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 286system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 287system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 288system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 289system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 290system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 291system.cpu.icache.writebacks::total 184976 # number of writebacks 292system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 293system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 294system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 295system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 296system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 297system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses | 284system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 285system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 286system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 287system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 288system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 289system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 290system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 291system.cpu.icache.writebacks::total 184976 # number of writebacks 292system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 293system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 294system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 295system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 296system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 297system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses |
| 298system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles 299system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles 300system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles 301system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles 302system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles 303system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles | 298system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2657728500 # number of ReadReq MSHR miss cycles 299system.cpu.icache.ReadReq_mshr_miss_latency::total 2657728500 # number of ReadReq MSHR miss cycles 300system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2657728500 # number of demand (read+write) MSHR miss cycles 301system.cpu.icache.demand_mshr_miss_latency::total 2657728500 # number of demand (read+write) MSHR miss cycles 302system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2657728500 # number of overall MSHR miss cycles 303system.cpu.icache.overall_mshr_miss_latency::total 2657728500 # number of overall MSHR miss cycles |
| 304system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses 305system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses 306system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses 307system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses 308system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 309system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses | 304system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses 305system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses 306system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses 307system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses 308system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 309system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses |
| 310system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency 311system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency 312system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 313system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 314system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 315system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 316system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states 317system.cpu.l2cache.tags.replacements 99022 # number of replacements 318system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use 319system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. 320system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. 321system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. 322system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 323system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor 324system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor 325system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor 326system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy 327system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy 328system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy 329system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy 330system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id 331system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 332system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id 333system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id 334system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id 335system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id 336system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id 337system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses 338system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses 339system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states 340system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits 341system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits | 310system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14210.628048 # average ReadReq mshr miss latency 311system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14210.628048 # average ReadReq mshr miss latency 312system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency 313system.cpu.icache.demand_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency 314system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency 315system.cpu.icache.overall_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency 316system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 317system.cpu.l2cache.tags.replacements 99926 # number of replacements 318system.cpu.l2cache.tags.tagsinuse 32138.485238 # Cycle average of tags in use 319system.cpu.l2cache.tags.total_refs 536406 # Total number of references to valid blocks. 320system.cpu.l2cache.tags.sampled_refs 132694 # Sample count of references to valid blocks. 321system.cpu.l2cache.tags.avg_refs 4.042428 # Average number of references to valid blocks. 322system.cpu.l2cache.tags.warmup_cycle 26729442000 # Cycle when the warmup percentage was hit. 323system.cpu.l2cache.tags.occ_blocks::writebacks 711.528666 # Average occupied blocks per requestor 324system.cpu.l2cache.tags.occ_blocks::cpu.inst 3108.349977 # Average occupied blocks per requestor 325system.cpu.l2cache.tags.occ_blocks::cpu.data 28318.606595 # Average occupied blocks per requestor 326system.cpu.l2cache.tags.occ_percent::writebacks 0.021714 # Average percentage of cache occupancy 327system.cpu.l2cache.tags.occ_percent::cpu.inst 0.094859 # Average percentage of cache occupancy 328system.cpu.l2cache.tags.occ_percent::cpu.data 0.864215 # Average percentage of cache occupancy 329system.cpu.l2cache.tags.occ_percent::total 0.980789 # Average percentage of cache occupancy 330system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 331system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id 332system.cpu.l2cache.tags.age_task_id_blocks_1024::1 570 # Occupied blocks per task id 333system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10913 # Occupied blocks per task id 334system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20279 # Occupied blocks per task id 335system.cpu.l2cache.tags.age_task_id_blocks_1024::4 818 # Occupied blocks per task id 336system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 337system.cpu.l2cache.tags.tag_accesses 5486262 # Number of tag accesses 338system.cpu.l2cache.tags.data_accesses 5486262 # Number of data accesses 339system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 340system.cpu.l2cache.WritebackDirty_hits::writebacks 123615 # number of WritebackDirty hits 341system.cpu.l2cache.WritebackDirty_hits::total 123615 # number of WritebackDirty hits |
| 342system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 343system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits | 342system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 343system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits |
| 344system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits 345system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits 346system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits 347system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits 348system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits 349system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits 350system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits 351system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits 352system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits 353system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits 354system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits 355system.cpu.l2cache.overall_hits::total 207181 # number of overall hits 356system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses 357system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses 358system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses 359system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses 360system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses 361system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses 362system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses 363system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses 364system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses 365system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses 366system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses 367system.cpu.l2cache.overall_misses::total 130522 # number of overall misses 368system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles 369system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles 370system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles 371system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles 372system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles 373system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles 374system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles 375system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles 376system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles 377system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles 378system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles 379system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles 380system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) 381system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) | 344system.cpu.l2cache.ReadExReq_hits::cpu.data 3868 # number of ReadExReq hits 345system.cpu.l2cache.ReadExReq_hits::total 3868 # number of ReadExReq hits 346system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178794 # number of ReadCleanReq hits 347system.cpu.l2cache.ReadCleanReq_hits::total 178794 # number of ReadCleanReq hits 348system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24230 # number of ReadSharedReq hits 349system.cpu.l2cache.ReadSharedReq_hits::total 24230 # number of ReadSharedReq hits 350system.cpu.l2cache.demand_hits::cpu.inst 178794 # number of demand (read+write) hits 351system.cpu.l2cache.demand_hits::cpu.data 28098 # number of demand (read+write) hits 352system.cpu.l2cache.demand_hits::total 206892 # number of demand (read+write) hits 353system.cpu.l2cache.overall_hits::cpu.inst 178794 # number of overall hits 354system.cpu.l2cache.overall_hits::cpu.data 28098 # number of overall hits 355system.cpu.l2cache.overall_hits::total 206892 # number of overall hits 356system.cpu.l2cache.ReadExReq_misses::cpu.data 101311 # number of ReadExReq misses 357system.cpu.l2cache.ReadExReq_misses::total 101311 # number of ReadExReq misses 358system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8230 # number of ReadCleanReq misses 359system.cpu.l2cache.ReadCleanReq_misses::total 8230 # number of ReadCleanReq misses 360system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21270 # number of ReadSharedReq misses 361system.cpu.l2cache.ReadSharedReq_misses::total 21270 # number of ReadSharedReq misses 362system.cpu.l2cache.demand_misses::cpu.inst 8230 # number of demand (read+write) misses 363system.cpu.l2cache.demand_misses::cpu.data 122581 # number of demand (read+write) misses 364system.cpu.l2cache.demand_misses::total 130811 # number of demand (read+write) misses 365system.cpu.l2cache.overall_misses::cpu.inst 8230 # number of overall misses 366system.cpu.l2cache.overall_misses::cpu.data 122581 # number of overall misses 367system.cpu.l2cache.overall_misses::total 130811 # number of overall misses 368system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6130000500 # number of ReadExReq miss cycles 369system.cpu.l2cache.ReadExReq_miss_latency::total 6130000500 # number of ReadExReq miss cycles 370system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 498248500 # number of ReadCleanReq miss cycles 371system.cpu.l2cache.ReadCleanReq_miss_latency::total 498248500 # number of ReadCleanReq miss cycles 372system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1286927500 # number of ReadSharedReq miss cycles 373system.cpu.l2cache.ReadSharedReq_miss_latency::total 1286927500 # number of ReadSharedReq miss cycles 374system.cpu.l2cache.demand_miss_latency::cpu.inst 498248500 # number of demand (read+write) miss cycles 375system.cpu.l2cache.demand_miss_latency::cpu.data 7416928000 # number of demand (read+write) miss cycles 376system.cpu.l2cache.demand_miss_latency::total 7915176500 # number of demand (read+write) miss cycles 377system.cpu.l2cache.overall_miss_latency::cpu.inst 498248500 # number of overall miss cycles 378system.cpu.l2cache.overall_miss_latency::cpu.data 7416928000 # number of overall miss cycles 379system.cpu.l2cache.overall_miss_latency::total 7915176500 # number of overall miss cycles 380system.cpu.l2cache.WritebackDirty_accesses::writebacks 123615 # number of WritebackDirty accesses(hits+misses) 381system.cpu.l2cache.WritebackDirty_accesses::total 123615 # number of WritebackDirty accesses(hits+misses) |
| 382system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) 383system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) 384system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) 385system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) 386system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) 387system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) 388system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) 389system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) 390system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses 391system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses 392system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses 393system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses 394system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses 395system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses | 382system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) 383system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) 384system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) 385system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) 386system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) 387system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) 388system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) 389system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) 390system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses 391system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses 392system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses 393system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses 394system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses 395system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses |
| 396system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses 397system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses 398system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses 399system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses 400system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses 401system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses 402system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses 403system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses 404system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses 405system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses 406system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses 407system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses 408system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency 409system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency 410system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency 411system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency 412system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency 413system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency 414system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency 415system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency 416system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency 417system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency 418system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency 419system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency | 396system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963225 # miss rate for ReadExReq accesses 397system.cpu.l2cache.ReadExReq_miss_rate::total 0.963225 # miss rate for ReadExReq accesses 398system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.044005 # miss rate for ReadCleanReq accesses 399system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.044005 # miss rate for ReadCleanReq accesses 400system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.467473 # miss rate for ReadSharedReq accesses 401system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.467473 # miss rate for ReadSharedReq accesses 402system.cpu.l2cache.demand_miss_rate::cpu.inst 0.044005 # miss rate for demand accesses 403system.cpu.l2cache.demand_miss_rate::cpu.data 0.813524 # miss rate for demand accesses 404system.cpu.l2cache.demand_miss_rate::total 0.387355 # miss rate for demand accesses 405system.cpu.l2cache.overall_miss_rate::cpu.inst 0.044005 # miss rate for overall accesses 406system.cpu.l2cache.overall_miss_rate::cpu.data 0.813524 # miss rate for overall accesses 407system.cpu.l2cache.overall_miss_rate::total 0.387355 # miss rate for overall accesses 408system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60506.761359 # average ReadExReq miss latency 409system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60506.761359 # average ReadExReq miss latency 410system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60540.522479 # average ReadCleanReq miss latency 411system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60540.522479 # average ReadCleanReq miss latency 412system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60504.348848 # average ReadSharedReq miss latency 413system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60504.348848 # average ReadSharedReq miss latency 414system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency 415system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency 416system.cpu.l2cache.demand_avg_miss_latency::total 60508.493170 # average overall miss latency 417system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency 418system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency 419system.cpu.l2cache.overall_avg_miss_latency::total 60508.493170 # average overall miss latency |
| 420system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 420system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 426system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks 427system.cpu.l2cache.writebacks::total 85270 # number of writebacks | 426system.cpu.l2cache.writebacks::writebacks 85566 # number of writebacks 427system.cpu.l2cache.writebacks::total 85566 # number of writebacks |
| 428system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 429system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses | 428system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 429system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses |
| 430system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses 431system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses 432system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses 433system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses 434system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses 435system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses 436system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses 437system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses 438system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses 439system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses 440system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses 441system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses 442system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles 443system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles 444system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles 445system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles 446system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles 447system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles 448system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles 449system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles 450system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles 451system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles 452system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles 453system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles | 430system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101311 # number of ReadExReq MSHR misses 431system.cpu.l2cache.ReadExReq_mshr_misses::total 101311 # number of ReadExReq MSHR misses 432system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8230 # number of ReadCleanReq MSHR misses 433system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8230 # number of ReadCleanReq MSHR misses 434system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21270 # number of ReadSharedReq MSHR misses 435system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21270 # number of ReadSharedReq MSHR misses 436system.cpu.l2cache.demand_mshr_misses::cpu.inst 8230 # number of demand (read+write) MSHR misses 437system.cpu.l2cache.demand_mshr_misses::cpu.data 122581 # number of demand (read+write) MSHR misses 438system.cpu.l2cache.demand_mshr_misses::total 130811 # number of demand (read+write) MSHR misses 439system.cpu.l2cache.overall_mshr_misses::cpu.inst 8230 # number of overall MSHR misses 440system.cpu.l2cache.overall_mshr_misses::cpu.data 122581 # number of overall MSHR misses 441system.cpu.l2cache.overall_mshr_misses::total 130811 # number of overall MSHR misses 442system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5116890500 # number of ReadExReq MSHR miss cycles 443system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5116890500 # number of ReadExReq MSHR miss cycles 444system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 415948500 # number of ReadCleanReq MSHR miss cycles 445system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 415948500 # number of ReadCleanReq MSHR miss cycles 446system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1074227500 # number of ReadSharedReq MSHR miss cycles 447system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1074227500 # number of ReadSharedReq MSHR miss cycles 448system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 415948500 # number of demand (read+write) MSHR miss cycles 449system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6191118000 # number of demand (read+write) MSHR miss cycles 450system.cpu.l2cache.demand_mshr_miss_latency::total 6607066500 # number of demand (read+write) MSHR miss cycles 451system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 415948500 # number of overall MSHR miss cycles 452system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6191118000 # number of overall MSHR miss cycles 453system.cpu.l2cache.overall_mshr_miss_latency::total 6607066500 # number of overall MSHR miss cycles |
| 454system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 455system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 454system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 455system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 456system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses 457system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses 458system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses 459system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses 460system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses 461system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses 462system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses 463system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses 464system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses 465system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses 466system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses 467system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses 468system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency 469system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency 470system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency 471system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency 472system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency 473system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency 474system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 475system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 476system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 477system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 478system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 479system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency | 456system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963225 # mshr miss rate for ReadExReq accesses 457system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963225 # mshr miss rate for ReadExReq accesses 458system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for ReadCleanReq accesses 459system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044005 # mshr miss rate for ReadCleanReq accesses 460system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.467473 # mshr miss rate for ReadSharedReq accesses 461system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.467473 # mshr miss rate for ReadSharedReq accesses 462system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for demand accesses 463system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for demand accesses 464system.cpu.l2cache.demand_mshr_miss_rate::total 0.387355 # mshr miss rate for demand accesses 465system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for overall accesses 466system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for overall accesses 467system.cpu.l2cache.overall_mshr_miss_rate::total 0.387355 # mshr miss rate for overall accesses 468system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50506.761359 # average ReadExReq mshr miss latency 469system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50506.761359 # average ReadExReq mshr miss latency 470system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479 # average ReadCleanReq mshr miss latency 471system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479 # average ReadCleanReq mshr miss latency 472system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848 # average ReadSharedReq mshr miss latency 473system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848 # average ReadSharedReq mshr miss latency 474system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency 475system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency 476system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency 477system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency 478system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency 479system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency |
| 480system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 481system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 482system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 480system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 481system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 482system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 483system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. 484system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 483system.cpu.toL2Bus.snoop_filter.tot_snoops 3837 # Total number of snoops made to the snoop filter. 484system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 485system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 485system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 486system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states | 486system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states |
| 487system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution | 487system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution |
| 488system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution | 488system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 # Transaction distribution |
| 489system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution | 489system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution |
| 490system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution | 490system.cpu.toL2Bus.trans_dist::CleanEvict 37328 # Transaction distribution |
| 491system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 492system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution 495system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) 496system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) 497system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) 498system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) | 491system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 492system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution 495system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) 496system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) 497system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) 498system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) |
| 499system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) 501system.cpu.toL2Bus.snoops 99022 # Total snoops (count) 502system.cpu.toL2Bus.snoopTraffic 5457280 # Total snoop traffic (bytes) 503system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram 504system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram 505system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram | 499system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 # Cumulative packet size per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_size::total 41362816 # Cumulative packet size per connected master and slave (bytes) 501system.cpu.toL2Bus.snoops 99926 # Total snoops (count) 502system.cpu.toL2Bus.snoopTraffic 5476224 # Total snoop traffic (bytes) 503system.cpu.toL2Bus.snoop_fanout::samples 437629 # Request fanout histogram 504system.cpu.toL2Bus.snoop_fanout::mean 0.008919 # Request fanout histogram 505system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 # Request fanout histogram |
| 506system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 506system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 507system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram | 507system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% # Request fanout histogram |
| 509system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 509system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 513system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram 514system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) | 513system.cpu.toL2Bus.snoop_fanout::total 437629 # Request fanout histogram 514system.cpu.toL2Bus.reqLayer0.occupancy 643222000 # Layer occupancy (ticks) |
| 515system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 516system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 517system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 518system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 519system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 515system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 516system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 517system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 518system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 519system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 520system.membus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states 521system.membus.trans_dist::ReadResp 29258 # Transaction distribution 522system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution 523system.membus.trans_dist::CleanEvict 10301 # Transaction distribution 524system.membus.trans_dist::ReadExReq 101264 # Transaction distribution 525system.membus.trans_dist::ReadExResp 101264 # Transaction distribution 526system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution 527system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) 528system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) 529system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) 530system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) | 520system.membus.snoop_filter.tot_requests 226995 # Total number of requests made to the snoop filter. 521system.membus.snoop_filter.hit_single_requests 96184 # Number of requests hitting in the snoop filter with a single holder of the requested data. 522system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 523system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 524system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 525system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 526system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 527system.membus.trans_dist::ReadResp 29500 # Transaction distribution 528system.membus.trans_dist::WritebackDirty 85566 # Transaction distribution 529system.membus.trans_dist::CleanEvict 10618 # Transaction distribution 530system.membus.trans_dist::ReadExReq 101311 # Transaction distribution 531system.membus.trans_dist::ReadExResp 101311 # Transaction distribution 532system.membus.trans_dist::ReadSharedReq 29500 # Transaction distribution 533system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 # Packet count per connected master and slave (bytes) 534system.membus.pkt_count::total 357806 # Packet count per connected master and slave (bytes) 535system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 # Cumulative packet size per connected master and slave (bytes) 536system.membus.pkt_size::total 13848128 # Cumulative packet size per connected master and slave (bytes) |
| 531system.membus.snoops 0 # Total snoops (count) 532system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 537system.membus.snoops 0 # Total snoops (count) 538system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 533system.membus.snoop_fanout::samples 226093 # Request fanout histogram | 539system.membus.snoop_fanout::samples 130811 # Request fanout histogram |
| 534system.membus.snoop_fanout::mean 0 # Request fanout histogram 535system.membus.snoop_fanout::stdev 0 # Request fanout histogram 536system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 540system.membus.snoop_fanout::mean 0 # Request fanout histogram 541system.membus.snoop_fanout::stdev 0 # Request fanout histogram 542system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 537system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram | 543system.membus.snoop_fanout::0 130811 100.00% 100.00% # Request fanout histogram |
| 538system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 539system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 540system.membus.snoop_fanout::min_value 0 # Request fanout histogram 541system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 544system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 545system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 546system.membus.snoop_fanout::min_value 0 # Request fanout histogram 547system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 542system.membus.snoop_fanout::total 226093 # Request fanout histogram 543system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) | 548system.membus.snoop_fanout::total 130811 # Request fanout histogram 549system.membus.reqLayer0.occupancy 570211500 # Layer occupancy (ticks) |
| 544system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) | 550system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 545system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) | 551system.membus.respLayer1.occupancy 654055000 # Layer occupancy (ticks) |
| 546system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 547 548---------- End Simulation Statistics ---------- | 552system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 553 554---------- End Simulation Statistics ---------- |