| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203116 # Number of seconds simulated 4sim_ticks 203115946500 # Number of ticks simulated 5final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203116 # Number of seconds simulated 4sim_ticks 203115946500 # Number of ticks simulated 5final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 790551 # Simulator instruction rate (inst/s) 8host_op_rate 800787 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1194752753 # Simulator tick rate (ticks/s) 10host_mem_usage 255284 # Number of bytes of host memory used 11host_seconds 170.01 # Real time elapsed on the host | 7host_inst_rate 1546845 # Simulator instruction rate (inst/s) 8host_op_rate 1566874 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2337732587 # Simulator tick rate (ticks/s) 10host_mem_usage 302284 # Number of bytes of host memory used 11host_seconds 86.89 # Real time elapsed on the host |
| 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 32system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) |
| 40system.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.workload.num_syscalls 1946 # Number of system calls | 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 43system.cpu.pwrStateResidencyTicks::ON 203115946500 # Cumulative time (in ticks) in various power states |
|
| 41system.cpu.numCycles 406231893 # number of cpu cycles simulated 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 134398959 # Number of instructions committed 45system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 48system.cpu.num_func_calls 1709332 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 91system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 92system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 93system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 94system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction 95system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 136293808 # Class of executed instruction | 44system.cpu.numCycles 406231893 # number of cpu cycles simulated 45system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 46system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47system.cpu.committedInsts 134398959 # Number of instructions committed 48system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 49system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 50system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 51system.cpu.num_func_calls 1709332 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 97system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction 98system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 136293808 # Class of executed instruction |
| 102system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 99system.cpu.dcache.tags.replacements 146583 # number of replacements 100system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use 101system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 102system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 103system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. 104system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. 105system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor 106system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy 107system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id 112system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 113system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 114system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses | 103system.cpu.dcache.tags.replacements 146583 # number of replacements 104system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use 105system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 106system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 107system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. 108system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. 109system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor 110system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy 112system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id 116system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 117system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 118system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses |
| 119system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 115system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency 216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency 218system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 220system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 222system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency | 120system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 124system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 125system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 126system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 127system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency 221system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency 222system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency 223system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency |
| 228system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 223system.cpu.icache.tags.replacements 184976 # number of replacements 224system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use 225system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 226system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 227system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 228system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. 229system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor 230system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy 231system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 238system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 239system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 240system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses | 229system.cpu.icache.tags.replacements 184976 # number of replacements 230system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use 231system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 232system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 233system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 234system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. 235system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor 236system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy 237system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy 238system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id 241system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 242system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 243system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 244system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 245system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 246system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses |
| 247system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 241system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 242system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 243system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 244system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 245system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 246system.cpu.icache.overall_hits::total 134366557 # number of overall hits 247system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 248system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 301system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 302system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency 304system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 306system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 308system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency | 248system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 249system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 250system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 251system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 252system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 253system.cpu.icache.overall_hits::total 134366557 # number of overall hits 254system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 255system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 308system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 309system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 310system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency 311system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency 312system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 313system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 314system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 315system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency |
| 316system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 309system.cpu.l2cache.tags.replacements 99022 # number of replacements 310system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use 311system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. 312system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. 313system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. 314system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 315system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor 316system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 323system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id 328system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id 329system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses 330system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses | 317system.cpu.l2cache.tags.replacements 99022 # number of replacements 318system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use 319system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. 320system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. 321system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. 322system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 323system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor 324system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 331system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 332system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id 333system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id 334system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id 335system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id 336system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id 337system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses 338system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses |
| 339system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
|
| 331system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits 332system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits 333system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 334system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits 335system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits 336system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits 337system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits 338system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 469system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 470system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 471system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 472system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 473system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 474system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. 475system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 476system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 340system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits 341system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits 342system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 343system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits 344system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits 345system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits 346system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits 347system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 478system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 479system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 480system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 481system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 482system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 483system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. 484system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 485system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 486system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
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| 477system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 484system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 501system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram 503system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) 504system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 505system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 506system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 507system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 508system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 487system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 488system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution 489system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution 490system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution 491system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 492system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 511system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram 513system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) 514system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 515system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 516system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 517system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 518system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 519system.membus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states |
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| 509system.membus.trans_dist::ReadResp 29258 # Transaction distribution 510system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution 511system.membus.trans_dist::CleanEvict 10301 # Transaction distribution 512system.membus.trans_dist::ReadExReq 101264 # Transaction distribution 513system.membus.trans_dist::ReadExResp 101264 # Transaction distribution 514system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution 515system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) 516system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 520system.membus.trans_dist::ReadResp 29258 # Transaction distribution 521system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution 522system.membus.trans_dist::CleanEvict 10301 # Transaction distribution 523system.membus.trans_dist::ReadExReq 101264 # Transaction distribution 524system.membus.trans_dist::ReadExResp 101264 # Transaction distribution 525system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution 526system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) 527system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden --- |