| stats.txt (11388:bd4125134e77) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203116 # Number of seconds simulated 4sim_ticks 203115946500 # Number of ticks simulated 5final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203116 # Number of seconds simulated 4sim_ticks 203115946500 # Number of ticks simulated 5final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 864116 # Simulator instruction rate (inst/s) 8host_op_rate 875304 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1305930078 # Simulator tick rate (ticks/s) 10host_mem_usage 235576 # Number of bytes of host memory used 11host_seconds 155.53 # Real time elapsed on the host | 7host_inst_rate 1277402 # Simulator instruction rate (inst/s) 8host_op_rate 1293942 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1930526358 # Simulator tick rate (ticks/s) 10host_mem_usage 259920 # Number of bytes of host memory used 11host_seconds 105.21 # Real time elapsed on the host |
| 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory --- 153 unchanged lines hidden (view full) --- 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency 175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory --- 153 unchanged lines hidden (view full) --- 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency 175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 181system.cpu.dcache.fast_writes 0 # number of fast writes performed 182system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 183system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks 184system.cpu.dcache.writebacks::total 123865 # number of writebacks 185system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 186system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 187system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 189system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 190system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 217system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency 218system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency 219system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency 220system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency 221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency | 181system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks 182system.cpu.dcache.writebacks::total 123865 # number of writebacks 183system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 184system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 186system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 187system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 188system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency 216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency 217system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency 218system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency 219system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 220system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency 221system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency 222system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency |
| 225system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 226system.cpu.icache.tags.replacements 184976 # number of replacements 227system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use 228system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 229system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 230system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 231system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. 232system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor 233system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 278system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency 279system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency 280system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 281system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 283system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 284system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 285system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 223system.cpu.icache.tags.replacements 184976 # number of replacements 224system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use 225system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 226system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 227system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 228system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. 229system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor 230system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 275system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency 276system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency 277system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 282system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 286system.cpu.icache.fast_writes 0 # number of fast writes performed 287system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 288system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 289system.cpu.icache.writebacks::total 184976 # number of writebacks 290system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 291system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 292system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 293system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 294system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 295system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 306system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 307system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 308system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency 309system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency 310system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 311system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 313system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency | 283system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 284system.cpu.icache.writebacks::total 184976 # number of writebacks 285system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 286system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 287system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 288system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 289system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 290system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 301system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 302system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency 304system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 306system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency 308system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency |
| 314system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 315system.cpu.l2cache.tags.replacements 99022 # number of replacements 316system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use 317system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. 318system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. 319system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. 320system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 321system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 415system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency 416system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency 417system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 418system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 420system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 421system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 422system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 309system.cpu.l2cache.tags.replacements 99022 # number of replacements 310system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use 311system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. 312system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. 313system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. 314system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 315system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor 316system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 409system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency 410system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency 411system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 423system.cpu.l2cache.fast_writes 0 # number of fast writes performed 424system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 425system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks 426system.cpu.l2cache.writebacks::total 85270 # number of writebacks 427system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 428system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 429system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses 430system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses 431system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses 432system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 471system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency 472system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency 473system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 474system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 475system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 476system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 477system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 478system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency | 417system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks 418system.cpu.l2cache.writebacks::total 85270 # number of writebacks 419system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 420system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 421system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses 422system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses 423system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses 424system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 463system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency 464system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 466system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 467system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency 468system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency 469system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency 470system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency |
| 479system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 480system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 481system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 482system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 483system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. 484system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 485system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 486system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 487system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution --- 57 unchanged lines hidden --- | 471system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 472system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 473system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 474system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. 475system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 476system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 477system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution --- 57 unchanged lines hidden --- |