4,5c4,5
< sim_ticks 202232894500 # Number of ticks simulated
< final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 202232960500 # Number of ticks simulated
> final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1204132 # Simulator instruction rate (inst/s)
< host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1811881435 # Simulator tick rate (ticks/s)
< host_mem_usage 302340 # Number of bytes of host memory used
< host_seconds 111.61 # Real time elapsed on the host
---
> host_inst_rate 1135828 # Simulator instruction rate (inst/s)
> host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1709104516 # Simulator tick rate (ticks/s)
> host_mem_usage 304720 # Number of bytes of host memory used
> host_seconds 118.33 # Real time elapsed on the host
28,38c28,38
< system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s)
41c41
< system.cpu.numCycles 404465789 # number of cpu cycles simulated
---
> system.cpu.numCycles 404465921 # number of cpu cycles simulated
60c60
< system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles
100c100
< system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use
104,105c104,105
< system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor
135,136c135,136
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles
141,144c141,144
< system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles
165,166c165,166
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency
171,174c171,174
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency
195,196c195,196
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles
201,204c201,204
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles
215,216c215,216
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency
221,224c221,224
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
227c227
< system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use
231,232c231,232
< system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor
256,261c256,261
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles
274,279c274,279
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency
294,299c294,299
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles
306,311c306,311
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency
314c314
< system.cpu.l2cache.tags.tagsinuse 30848.444766 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 30848.444719 # Cycle average of tags in use
319,321c319,321
< system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828940 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810202 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805624 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810369 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805642 # Average occupied blocks per requestor
473a474,479
> system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 3540 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3540 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
489,490c495,496
< system.cpu.toL2Bus.snoop_fanout::mean 1.128066 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.334163 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.004784 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.069001 # Request fanout histogram
492,494c498,500
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 669260 87.19% 87.19% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 98298 12.81% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 763886 99.52% 99.52% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3672 0.48% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
496,497c502,503
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
< sim_ticks 202232894500 # Number of ticks simulated
< final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 202232960500 # Number of ticks simulated
> final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1204132 # Simulator instruction rate (inst/s)
< host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1811881435 # Simulator tick rate (ticks/s)
< host_mem_usage 302340 # Number of bytes of host memory used
< host_seconds 111.61 # Real time elapsed on the host
---
> host_inst_rate 1135828 # Simulator instruction rate (inst/s)
> host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1709104516 # Simulator tick rate (ticks/s)
> host_mem_usage 304720 # Number of bytes of host memory used
> host_seconds 118.33 # Real time elapsed on the host
28,38c28,38
< system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s)
41c41
< system.cpu.numCycles 404465789 # number of cpu cycles simulated
---
> system.cpu.numCycles 404465921 # number of cpu cycles simulated
60c60
< system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles
100c100
< system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use
104,105c104,105
< system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor
135,136c135,136
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles
141,144c141,144
< system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles
165,166c165,166
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency
171,174c171,174
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency
195,196c195,196
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles
201,204c201,204
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles
215,216c215,216
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency
221,224c221,224
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
227c227
< system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use
231,232c231,232
< system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor
256,261c256,261
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles
274,279c274,279
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency
294,299c294,299
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles
306,311c306,311
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency
314c314
< system.cpu.l2cache.tags.tagsinuse 30848.444766 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 30848.444719 # Cycle average of tags in use
319,321c319,321
< system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828940 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810202 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805624 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810369 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805642 # Average occupied blocks per requestor
473a474,479
> system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 3540 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3540 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
489,490c495,496
< system.cpu.toL2Bus.snoop_fanout::mean 1.128066 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.334163 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.004784 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.069001 # Request fanout histogram
492,494c498,500
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 669260 87.19% 87.19% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 98298 12.81% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 763886 99.52% 99.52% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3672 0.48% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
496,497c502,503
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram