Cross Reference: /gem5/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt

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stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203261 # Number of seconds simulated 4sim_ticks 203260902500 # Number of ticks simulated 5final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1825324 # Simulator instruction rate (inst/s) 8host_op_rate 1848958 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2760562270 # Simulator tick rate (ticks/s) 10host_mem_usage 261500 # Number of bytes of host memory used 11host_seconds 73.63 # Real time elapsed on the host 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 526720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7845184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8371904 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 526720 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 526720 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5476224 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5476224 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8230 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 122581 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 130811 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 85566 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 85566 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 2591349 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 38596621 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 41187970 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 2591349 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 2591349 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 26941846 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 26941846 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 26941846 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 2591349 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 38596621 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 68129817 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.203261 # Number of seconds simulated 4sim_ticks 203260902500 # Number of ticks simulated 5final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1825324 # Simulator instruction rate (inst/s) 8host_op_rate 1848958 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2760562270 # Simulator tick rate (ticks/s) 10host_mem_usage 261500 # Number of bytes of host memory used 11host_seconds 73.63 # Real time elapsed on the host 12sim_insts 134398959 # Number of instructions simulated 13sim_ops 136139187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 526720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7845184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8371904 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 526720 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 526720 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5476224 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5476224 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8230 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 122581 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 130811 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 85566 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 85566 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 2591349 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 38596621 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 41187970 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 2591349 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 2591349 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 26941846 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 26941846 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 26941846 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 2591349 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 38596621 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 68129817 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks
42system.cpu.workload.num_syscalls 1946 # Number of system calls	42system.cpu.workload.numSyscalls 1946 # Number of system calls
43system.cpu.pwrStateResidencyTicks::ON 203260902500 # Cumulative time (in ticks) in various power states 44system.cpu.numCycles 406521805 # number of cpu cycles simulated 45system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 46system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47system.cpu.committedInsts 134398959 # Number of instructions committed 48system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 49system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 50system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 51system.cpu.num_func_calls 1709332 # number of times a function call or return occured 52system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls 53system.cpu.num_int_insts 115187757 # number of integer instructions 54system.cpu.num_fp_insts 2326976 # number of float instructions 55system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read 56system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written 57system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read 58system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 59system.cpu.num_mem_refs 58160261 # number of memory refs 60system.cpu.num_load_insts 37275864 # Number of load instructions 61system.cpu.num_store_insts 20884397 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 406521804.998000 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 12719094 # Number of branches fetched 67system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 68system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction 69system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction 75system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction 76system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction 77system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction 78system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction 79system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction 80system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction 81system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction 82system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction 83system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction 84system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction 85system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction 86system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction 87system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction 88system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction 89system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction 90system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction 91system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction 92system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction 93system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction 94system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction 95system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction 96system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 97system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 98system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 99system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction 100system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction 101system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction 102system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction 103system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 104system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 105system.cpu.op_class::total 136293808 # Class of executed instruction 106system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 107system.cpu.dcache.tags.replacements 146583 # number of replacements 108system.cpu.dcache.tags.tagsinuse 4087.215868 # Cycle average of tags in use 109system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 110system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 111system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. 112system.cpu.dcache.tags.warmup_cycle 829975500 # Cycle when the warmup percentage was hit. 113system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868 # Average occupied blocks per requestor 114system.cpu.dcache.tags.occ_percent::cpu.data 0.997855 # Average percentage of cache occupancy 115system.cpu.dcache.tags.occ_percent::total 0.997855 # Average percentage of cache occupancy 116system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 117system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 118system.cpu.dcache.tags.age_task_id_blocks_1024::1 462 # Occupied blocks per task id 119system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598 # Occupied blocks per task id 120system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 121system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 122system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses 123system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 124system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 125system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 126system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 127system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 128system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 129system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 130system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 131system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits 132system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits 133system.cpu.dcache.overall_hits::total 57944940 # number of overall hits 134system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses 135system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses 136system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 137system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 138system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 139system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 140system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses 141system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses 142system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses 143system.cpu.dcache.overall_misses::total 150664 # number of overall misses 144system.cpu.dcache.ReadReq_miss_latency::cpu.data 1655141000 # number of ReadReq miss cycles 145system.cpu.dcache.ReadReq_miss_latency::total 1655141000 # number of ReadReq miss cycles 146system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433166000 # number of WriteReq miss cycles 147system.cpu.dcache.WriteReq_miss_latency::total 6433166000 # number of WriteReq miss cycles 148system.cpu.dcache.SwapReq_miss_latency::cpu.data 446000 # number of SwapReq miss cycles 149system.cpu.dcache.SwapReq_miss_latency::total 446000 # number of SwapReq miss cycles 150system.cpu.dcache.demand_miss_latency::cpu.data 8088307000 # number of demand (read+write) miss cycles 151system.cpu.dcache.demand_miss_latency::total 8088307000 # number of demand (read+write) miss cycles 152system.cpu.dcache.overall_miss_latency::cpu.data 8088307000 # number of overall miss cycles 153system.cpu.dcache.overall_miss_latency::total 8088307000 # number of overall miss cycles 154system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 155system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 156system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 157system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 158system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 159system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 160system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 168system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 169system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 170system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 171system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 172system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 173system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses 174system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36376.725275 # average ReadReq miss latency 175system.cpu.dcache.ReadReq_avg_miss_latency::total 36376.725275 # average ReadReq miss latency 176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61172.701685 # average WriteReq miss latency 177system.cpu.dcache.WriteReq_avg_miss_latency::total 61172.701685 # average WriteReq miss latency 178system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29733.333333 # average SwapReq miss latency 179system.cpu.dcache.SwapReq_avg_miss_latency::total 29733.333333 # average SwapReq miss latency 180system.cpu.dcache.demand_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency 181system.cpu.dcache.demand_avg_miss_latency::total 53684.403706 # average overall miss latency 182system.cpu.dcache.overall_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency 183system.cpu.dcache.overall_avg_miss_latency::total 53684.403706 # average overall miss latency 184system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 186system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 187system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 188system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 190system.cpu.dcache.writebacks::writebacks 123615 # number of writebacks 191system.cpu.dcache.writebacks::total 123615 # number of writebacks 192system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 193system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 194system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 195system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 196system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 197system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 198system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses 199system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses 200system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses 201system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses 202system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1609641000 # number of ReadReq MSHR miss cycles 203system.cpu.dcache.ReadReq_mshr_miss_latency::total 1609641000 # number of ReadReq MSHR miss cycles 204system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6328002000 # number of WriteReq MSHR miss cycles 205system.cpu.dcache.WriteReq_mshr_miss_latency::total 6328002000 # number of WriteReq MSHR miss cycles 206system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 431000 # number of SwapReq MSHR miss cycles 207system.cpu.dcache.SwapReq_mshr_miss_latency::total 431000 # number of SwapReq MSHR miss cycles 208system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7937643000 # number of demand (read+write) MSHR miss cycles 209system.cpu.dcache.demand_mshr_miss_latency::total 7937643000 # number of demand (read+write) MSHR miss cycles 210system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7937643000 # number of overall MSHR miss cycles 211system.cpu.dcache.overall_mshr_miss_latency::total 7937643000 # number of overall MSHR miss cycles 212system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 213system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 214system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 215system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 216system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 217system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 218system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 219system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 220system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 221system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses 222system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35376.725275 # average ReadReq mshr miss latency 223system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35376.725275 # average ReadReq mshr miss latency 224system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60172.701685 # average WriteReq mshr miss latency 225system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60172.701685 # average WriteReq mshr miss latency 226system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28733.333333 # average SwapReq mshr miss latency 227system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28733.333333 # average SwapReq mshr miss latency 228system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency 229system.cpu.dcache.demand_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency 230system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency 231system.cpu.dcache.overall_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency 232system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 233system.cpu.icache.tags.replacements 184976 # number of replacements 234system.cpu.icache.tags.tagsinuse 2004.091327 # Cycle average of tags in use 235system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 236system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 237system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 238system.cpu.icache.tags.warmup_cycle 144688165500 # Cycle when the warmup percentage was hit. 239system.cpu.icache.tags.occ_blocks::cpu.inst 2004.091327 # Average occupied blocks per requestor 240system.cpu.icache.tags.occ_percent::cpu.inst 0.978560 # Average percentage of cache occupancy 241system.cpu.icache.tags.occ_percent::total 0.978560 # Average percentage of cache occupancy 242system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 243system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 244system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 245system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 246system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 247system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 248system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 249system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 250system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses 251system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 252system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 253system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 254system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 255system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 256system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 257system.cpu.icache.overall_hits::total 134366557 # number of overall hits 258system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 259system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 260system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 261system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 262system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 263system.cpu.icache.overall_misses::total 187024 # number of overall misses 264system.cpu.icache.ReadReq_miss_latency::cpu.inst 2844752500 # number of ReadReq miss cycles 265system.cpu.icache.ReadReq_miss_latency::total 2844752500 # number of ReadReq miss cycles 266system.cpu.icache.demand_miss_latency::cpu.inst 2844752500 # number of demand (read+write) miss cycles 267system.cpu.icache.demand_miss_latency::total 2844752500 # number of demand (read+write) miss cycles 268system.cpu.icache.overall_miss_latency::cpu.inst 2844752500 # number of overall miss cycles 269system.cpu.icache.overall_miss_latency::total 2844752500 # number of overall miss cycles 270system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) 271system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) 272system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses 273system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses 274system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses 275system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses 276system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 277system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 278system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 279system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 280system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 281system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses 282system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15210.628048 # average ReadReq miss latency 283system.cpu.icache.ReadReq_avg_miss_latency::total 15210.628048 # average ReadReq miss latency 284system.cpu.icache.demand_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency 285system.cpu.icache.demand_avg_miss_latency::total 15210.628048 # average overall miss latency 286system.cpu.icache.overall_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency 287system.cpu.icache.overall_avg_miss_latency::total 15210.628048 # average overall miss latency 288system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 290system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 291system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 292system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 293system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 294system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 295system.cpu.icache.writebacks::total 184976 # number of writebacks 296system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 297system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 298system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 299system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 300system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 301system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses 302system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2657728500 # number of ReadReq MSHR miss cycles 303system.cpu.icache.ReadReq_mshr_miss_latency::total 2657728500 # number of ReadReq MSHR miss cycles 304system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2657728500 # number of demand (read+write) MSHR miss cycles 305system.cpu.icache.demand_mshr_miss_latency::total 2657728500 # number of demand (read+write) MSHR miss cycles 306system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2657728500 # number of overall MSHR miss cycles 307system.cpu.icache.overall_mshr_miss_latency::total 2657728500 # number of overall MSHR miss cycles 308system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses 309system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses 310system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses 311system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses 312system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 313system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 314system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14210.628048 # average ReadReq mshr miss latency 315system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14210.628048 # average ReadReq mshr miss latency 316system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency 317system.cpu.icache.demand_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency 318system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency 319system.cpu.icache.overall_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency 320system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 321system.cpu.l2cache.tags.replacements 99926 # number of replacements 322system.cpu.l2cache.tags.tagsinuse 32138.485238 # Cycle average of tags in use 323system.cpu.l2cache.tags.total_refs 536406 # Total number of references to valid blocks. 324system.cpu.l2cache.tags.sampled_refs 132694 # Sample count of references to valid blocks. 325system.cpu.l2cache.tags.avg_refs 4.042428 # Average number of references to valid blocks. 326system.cpu.l2cache.tags.warmup_cycle 26729442000 # Cycle when the warmup percentage was hit. 327system.cpu.l2cache.tags.occ_blocks::writebacks 711.528666 # Average occupied blocks per requestor 328system.cpu.l2cache.tags.occ_blocks::cpu.inst 3108.349977 # Average occupied blocks per requestor 329system.cpu.l2cache.tags.occ_blocks::cpu.data 28318.606595 # Average occupied blocks per requestor 330system.cpu.l2cache.tags.occ_percent::writebacks 0.021714 # Average percentage of cache occupancy 331system.cpu.l2cache.tags.occ_percent::cpu.inst 0.094859 # Average percentage of cache occupancy 332system.cpu.l2cache.tags.occ_percent::cpu.data 0.864215 # Average percentage of cache occupancy 333system.cpu.l2cache.tags.occ_percent::total 0.980789 # Average percentage of cache occupancy 334system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 335system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id 336system.cpu.l2cache.tags.age_task_id_blocks_1024::1 570 # Occupied blocks per task id 337system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10913 # Occupied blocks per task id 338system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20279 # Occupied blocks per task id 339system.cpu.l2cache.tags.age_task_id_blocks_1024::4 818 # Occupied blocks per task id 340system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 341system.cpu.l2cache.tags.tag_accesses 5486262 # Number of tag accesses 342system.cpu.l2cache.tags.data_accesses 5486262 # Number of data accesses 343system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 344system.cpu.l2cache.WritebackDirty_hits::writebacks 123615 # number of WritebackDirty hits 345system.cpu.l2cache.WritebackDirty_hits::total 123615 # number of WritebackDirty hits 346system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 347system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits 348system.cpu.l2cache.ReadExReq_hits::cpu.data 3868 # number of ReadExReq hits 349system.cpu.l2cache.ReadExReq_hits::total 3868 # number of ReadExReq hits 350system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178794 # number of ReadCleanReq hits 351system.cpu.l2cache.ReadCleanReq_hits::total 178794 # number of ReadCleanReq hits 352system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24230 # number of ReadSharedReq hits 353system.cpu.l2cache.ReadSharedReq_hits::total 24230 # number of ReadSharedReq hits 354system.cpu.l2cache.demand_hits::cpu.inst 178794 # number of demand (read+write) hits 355system.cpu.l2cache.demand_hits::cpu.data 28098 # number of demand (read+write) hits 356system.cpu.l2cache.demand_hits::total 206892 # number of demand (read+write) hits 357system.cpu.l2cache.overall_hits::cpu.inst 178794 # number of overall hits 358system.cpu.l2cache.overall_hits::cpu.data 28098 # number of overall hits 359system.cpu.l2cache.overall_hits::total 206892 # number of overall hits 360system.cpu.l2cache.ReadExReq_misses::cpu.data 101311 # number of ReadExReq misses 361system.cpu.l2cache.ReadExReq_misses::total 101311 # number of ReadExReq misses 362system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8230 # number of ReadCleanReq misses 363system.cpu.l2cache.ReadCleanReq_misses::total 8230 # number of ReadCleanReq misses 364system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21270 # number of ReadSharedReq misses 365system.cpu.l2cache.ReadSharedReq_misses::total 21270 # number of ReadSharedReq misses 366system.cpu.l2cache.demand_misses::cpu.inst 8230 # number of demand (read+write) misses 367system.cpu.l2cache.demand_misses::cpu.data 122581 # number of demand (read+write) misses 368system.cpu.l2cache.demand_misses::total 130811 # number of demand (read+write) misses 369system.cpu.l2cache.overall_misses::cpu.inst 8230 # number of overall misses 370system.cpu.l2cache.overall_misses::cpu.data 122581 # number of overall misses 371system.cpu.l2cache.overall_misses::total 130811 # number of overall misses 372system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6130000500 # number of ReadExReq miss cycles 373system.cpu.l2cache.ReadExReq_miss_latency::total 6130000500 # number of ReadExReq miss cycles 374system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 498248500 # number of ReadCleanReq miss cycles 375system.cpu.l2cache.ReadCleanReq_miss_latency::total 498248500 # number of ReadCleanReq miss cycles 376system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1286927500 # number of ReadSharedReq miss cycles 377system.cpu.l2cache.ReadSharedReq_miss_latency::total 1286927500 # number of ReadSharedReq miss cycles 378system.cpu.l2cache.demand_miss_latency::cpu.inst 498248500 # number of demand (read+write) miss cycles 379system.cpu.l2cache.demand_miss_latency::cpu.data 7416928000 # number of demand (read+write) miss cycles 380system.cpu.l2cache.demand_miss_latency::total 7915176500 # number of demand (read+write) miss cycles 381system.cpu.l2cache.overall_miss_latency::cpu.inst 498248500 # number of overall miss cycles 382system.cpu.l2cache.overall_miss_latency::cpu.data 7416928000 # number of overall miss cycles 383system.cpu.l2cache.overall_miss_latency::total 7915176500 # number of overall miss cycles 384system.cpu.l2cache.WritebackDirty_accesses::writebacks 123615 # number of WritebackDirty accesses(hits+misses) 385system.cpu.l2cache.WritebackDirty_accesses::total 123615 # number of WritebackDirty accesses(hits+misses) 386system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) 387system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) 388system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) 389system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) 390system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) 391system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) 392system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) 393system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) 394system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses 395system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses 396system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses 397system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses 398system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses 399system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses 400system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963225 # miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_miss_rate::total 0.963225 # miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.044005 # miss rate for ReadCleanReq accesses 403system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.044005 # miss rate for ReadCleanReq accesses 404system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.467473 # miss rate for ReadSharedReq accesses 405system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.467473 # miss rate for ReadSharedReq accesses 406system.cpu.l2cache.demand_miss_rate::cpu.inst 0.044005 # miss rate for demand accesses 407system.cpu.l2cache.demand_miss_rate::cpu.data 0.813524 # miss rate for demand accesses 408system.cpu.l2cache.demand_miss_rate::total 0.387355 # miss rate for demand accesses 409system.cpu.l2cache.overall_miss_rate::cpu.inst 0.044005 # miss rate for overall accesses 410system.cpu.l2cache.overall_miss_rate::cpu.data 0.813524 # miss rate for overall accesses 411system.cpu.l2cache.overall_miss_rate::total 0.387355 # miss rate for overall accesses 412system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60506.761359 # average ReadExReq miss latency 413system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60506.761359 # average ReadExReq miss latency 414system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60540.522479 # average ReadCleanReq miss latency 415system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60540.522479 # average ReadCleanReq miss latency 416system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60504.348848 # average ReadSharedReq miss latency 417system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60504.348848 # average ReadSharedReq miss latency 418system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency 419system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency 420system.cpu.l2cache.demand_avg_miss_latency::total 60508.493170 # average overall miss latency 421system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency 422system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency 423system.cpu.l2cache.overall_avg_miss_latency::total 60508.493170 # average overall miss latency 424system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu.l2cache.writebacks::writebacks 85566 # number of writebacks 431system.cpu.l2cache.writebacks::total 85566 # number of writebacks 432system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 433system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 434system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101311 # number of ReadExReq MSHR misses 435system.cpu.l2cache.ReadExReq_mshr_misses::total 101311 # number of ReadExReq MSHR misses 436system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8230 # number of ReadCleanReq MSHR misses 437system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8230 # number of ReadCleanReq MSHR misses 438system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21270 # number of ReadSharedReq MSHR misses 439system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21270 # number of ReadSharedReq MSHR misses 440system.cpu.l2cache.demand_mshr_misses::cpu.inst 8230 # number of demand (read+write) MSHR misses 441system.cpu.l2cache.demand_mshr_misses::cpu.data 122581 # number of demand (read+write) MSHR misses 442system.cpu.l2cache.demand_mshr_misses::total 130811 # number of demand (read+write) MSHR misses 443system.cpu.l2cache.overall_mshr_misses::cpu.inst 8230 # number of overall MSHR misses 444system.cpu.l2cache.overall_mshr_misses::cpu.data 122581 # number of overall MSHR misses 445system.cpu.l2cache.overall_mshr_misses::total 130811 # number of overall MSHR misses 446system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5116890500 # number of ReadExReq MSHR miss cycles 447system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5116890500 # number of ReadExReq MSHR miss cycles 448system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 415948500 # number of ReadCleanReq MSHR miss cycles 449system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 415948500 # number of ReadCleanReq MSHR miss cycles 450system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1074227500 # number of ReadSharedReq MSHR miss cycles 451system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1074227500 # number of ReadSharedReq MSHR miss cycles 452system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 415948500 # number of demand (read+write) MSHR miss cycles 453system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6191118000 # number of demand (read+write) MSHR miss cycles 454system.cpu.l2cache.demand_mshr_miss_latency::total 6607066500 # number of demand (read+write) MSHR miss cycles 455system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 415948500 # number of overall MSHR miss cycles 456system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6191118000 # number of overall MSHR miss cycles 457system.cpu.l2cache.overall_mshr_miss_latency::total 6607066500 # number of overall MSHR miss cycles 458system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 459system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 460system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963225 # mshr miss rate for ReadExReq accesses 461system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963225 # mshr miss rate for ReadExReq accesses 462system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for ReadCleanReq accesses 463system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044005 # mshr miss rate for ReadCleanReq accesses 464system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.467473 # mshr miss rate for ReadSharedReq accesses 465system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.467473 # mshr miss rate for ReadSharedReq accesses 466system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for demand accesses 467system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for demand accesses 468system.cpu.l2cache.demand_mshr_miss_rate::total 0.387355 # mshr miss rate for demand accesses 469system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for overall accesses 470system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for overall accesses 471system.cpu.l2cache.overall_mshr_miss_rate::total 0.387355 # mshr miss rate for overall accesses 472system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50506.761359 # average ReadExReq mshr miss latency 473system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50506.761359 # average ReadExReq mshr miss latency 474system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479 # average ReadCleanReq mshr miss latency 475system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479 # average ReadCleanReq mshr miss latency 476system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848 # average ReadSharedReq mshr miss latency 477system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848 # average ReadSharedReq mshr miss latency 478system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency 479system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency 480system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency 481system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency 482system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency 483system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency 484system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 485system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 486system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 487system.cpu.toL2Bus.snoop_filter.tot_snoops 3837 # Total number of snoops made to the snoop filter. 488system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 489system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 490system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 491system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 492system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::CleanEvict 37328 # Transaction distribution 495system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 497system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 498system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution 499system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) 501system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) 502system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) 503system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 # Cumulative packet size per connected master and slave (bytes) 504system.cpu.toL2Bus.pkt_size::total 41362816 # Cumulative packet size per connected master and slave (bytes) 505system.cpu.toL2Bus.snoops 99926 # Total snoops (count) 506system.cpu.toL2Bus.snoopTraffic 5476224 # Total snoop traffic (bytes) 507system.cpu.toL2Bus.snoop_fanout::samples 437629 # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::mean 0.008919 # Request fanout histogram 509system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% # Request fanout histogram 513system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 514system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 515system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 516system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 517system.cpu.toL2Bus.snoop_fanout::total 437629 # Request fanout histogram 518system.cpu.toL2Bus.reqLayer0.occupancy 643222000 # Layer occupancy (ticks) 519system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 520system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 521system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 522system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 523system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 524system.membus.snoop_filter.tot_requests 226995 # Total number of requests made to the snoop filter. 525system.membus.snoop_filter.hit_single_requests 96184 # Number of requests hitting in the snoop filter with a single holder of the requested data. 526system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 527system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 528system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 529system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 530system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 531system.membus.trans_dist::ReadResp 29500 # Transaction distribution 532system.membus.trans_dist::WritebackDirty 85566 # Transaction distribution 533system.membus.trans_dist::CleanEvict 10618 # Transaction distribution 534system.membus.trans_dist::ReadExReq 101311 # Transaction distribution 535system.membus.trans_dist::ReadExResp 101311 # Transaction distribution 536system.membus.trans_dist::ReadSharedReq 29500 # Transaction distribution 537system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 # Packet count per connected master and slave (bytes) 538system.membus.pkt_count::total 357806 # Packet count per connected master and slave (bytes) 539system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 # Cumulative packet size per connected master and slave (bytes) 540system.membus.pkt_size::total 13848128 # Cumulative packet size per connected master and slave (bytes) 541system.membus.snoops 0 # Total snoops (count) 542system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 543system.membus.snoop_fanout::samples 130811 # Request fanout histogram 544system.membus.snoop_fanout::mean 0 # Request fanout histogram 545system.membus.snoop_fanout::stdev 0 # Request fanout histogram 546system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 547system.membus.snoop_fanout::0 130811 100.00% 100.00% # Request fanout histogram 548system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 549system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 550system.membus.snoop_fanout::min_value 0 # Request fanout histogram 551system.membus.snoop_fanout::max_value 0 # Request fanout histogram 552system.membus.snoop_fanout::total 130811 # Request fanout histogram 553system.membus.reqLayer0.occupancy 570211500 # Layer occupancy (ticks) 554system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 555system.membus.respLayer1.occupancy 654055000 # Layer occupancy (ticks) 556system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 557 558---------- End Simulation Statistics ----------	43system.cpu.pwrStateResidencyTicks::ON 203260902500 # Cumulative time (in ticks) in various power states 44system.cpu.numCycles 406521805 # number of cpu cycles simulated 45system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 46system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47system.cpu.committedInsts 134398959 # Number of instructions committed 48system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed 49system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses 50system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses 51system.cpu.num_func_calls 1709332 # number of times a function call or return occured 52system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls 53system.cpu.num_int_insts 115187757 # number of integer instructions 54system.cpu.num_fp_insts 2326976 # number of float instructions 55system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read 56system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written 57system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read 58system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 59system.cpu.num_mem_refs 58160261 # number of memory refs 60system.cpu.num_load_insts 37275864 # Number of load instructions 61system.cpu.num_store_insts 20884397 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 406521804.998000 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 12719094 # Number of branches fetched 67system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 68system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction 69system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction 75system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction 76system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction 77system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction 78system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction 79system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction 80system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction 81system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction 82system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction 83system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction 84system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction 85system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction 86system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction 87system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction 88system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction 89system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction 90system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction 91system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction 92system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction 93system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction 94system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction 95system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction 96system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 97system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 98system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 99system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction 100system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction 101system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction 102system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction 103system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 104system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 105system.cpu.op_class::total 136293808 # Class of executed instruction 106system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 107system.cpu.dcache.tags.replacements 146583 # number of replacements 108system.cpu.dcache.tags.tagsinuse 4087.215868 # Cycle average of tags in use 109system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. 110system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. 111system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. 112system.cpu.dcache.tags.warmup_cycle 829975500 # Cycle when the warmup percentage was hit. 113system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868 # Average occupied blocks per requestor 114system.cpu.dcache.tags.occ_percent::cpu.data 0.997855 # Average percentage of cache occupancy 115system.cpu.dcache.tags.occ_percent::total 0.997855 # Average percentage of cache occupancy 116system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 117system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 118system.cpu.dcache.tags.age_task_id_blocks_1024::1 462 # Occupied blocks per task id 119system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598 # Occupied blocks per task id 120system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 121system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses 122system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses 123system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 124system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits 125system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits 126system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 127system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 128system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 129system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 130system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits 131system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits 132system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits 133system.cpu.dcache.overall_hits::total 57944940 # number of overall hits 134system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses 135system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses 136system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 137system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 138system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 139system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 140system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses 141system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses 142system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses 143system.cpu.dcache.overall_misses::total 150664 # number of overall misses 144system.cpu.dcache.ReadReq_miss_latency::cpu.data 1655141000 # number of ReadReq miss cycles 145system.cpu.dcache.ReadReq_miss_latency::total 1655141000 # number of ReadReq miss cycles 146system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433166000 # number of WriteReq miss cycles 147system.cpu.dcache.WriteReq_miss_latency::total 6433166000 # number of WriteReq miss cycles 148system.cpu.dcache.SwapReq_miss_latency::cpu.data 446000 # number of SwapReq miss cycles 149system.cpu.dcache.SwapReq_miss_latency::total 446000 # number of SwapReq miss cycles 150system.cpu.dcache.demand_miss_latency::cpu.data 8088307000 # number of demand (read+write) miss cycles 151system.cpu.dcache.demand_miss_latency::total 8088307000 # number of demand (read+write) miss cycles 152system.cpu.dcache.overall_miss_latency::cpu.data 8088307000 # number of overall miss cycles 153system.cpu.dcache.overall_miss_latency::total 8088307000 # number of overall miss cycles 154system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 155system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 156system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 157system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 158system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 159system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 160system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 168system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 169system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 170system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 171system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 172system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 173system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses 174system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36376.725275 # average ReadReq miss latency 175system.cpu.dcache.ReadReq_avg_miss_latency::total 36376.725275 # average ReadReq miss latency 176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61172.701685 # average WriteReq miss latency 177system.cpu.dcache.WriteReq_avg_miss_latency::total 61172.701685 # average WriteReq miss latency 178system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29733.333333 # average SwapReq miss latency 179system.cpu.dcache.SwapReq_avg_miss_latency::total 29733.333333 # average SwapReq miss latency 180system.cpu.dcache.demand_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency 181system.cpu.dcache.demand_avg_miss_latency::total 53684.403706 # average overall miss latency 182system.cpu.dcache.overall_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency 183system.cpu.dcache.overall_avg_miss_latency::total 53684.403706 # average overall miss latency 184system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 186system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 187system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 188system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 190system.cpu.dcache.writebacks::writebacks 123615 # number of writebacks 191system.cpu.dcache.writebacks::total 123615 # number of writebacks 192system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses 193system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses 194system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 195system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 196system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 197system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 198system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses 199system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses 200system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses 201system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses 202system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1609641000 # number of ReadReq MSHR miss cycles 203system.cpu.dcache.ReadReq_mshr_miss_latency::total 1609641000 # number of ReadReq MSHR miss cycles 204system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6328002000 # number of WriteReq MSHR miss cycles 205system.cpu.dcache.WriteReq_mshr_miss_latency::total 6328002000 # number of WriteReq MSHR miss cycles 206system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 431000 # number of SwapReq MSHR miss cycles 207system.cpu.dcache.SwapReq_mshr_miss_latency::total 431000 # number of SwapReq MSHR miss cycles 208system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7937643000 # number of demand (read+write) MSHR miss cycles 209system.cpu.dcache.demand_mshr_miss_latency::total 7937643000 # number of demand (read+write) MSHR miss cycles 210system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7937643000 # number of overall MSHR miss cycles 211system.cpu.dcache.overall_mshr_miss_latency::total 7937643000 # number of overall MSHR miss cycles 212system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 213system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 214system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 215system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 216system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 217system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 218system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 219system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 220system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 221system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses 222system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35376.725275 # average ReadReq mshr miss latency 223system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35376.725275 # average ReadReq mshr miss latency 224system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60172.701685 # average WriteReq mshr miss latency 225system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60172.701685 # average WriteReq mshr miss latency 226system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28733.333333 # average SwapReq mshr miss latency 227system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28733.333333 # average SwapReq mshr miss latency 228system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency 229system.cpu.dcache.demand_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency 230system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency 231system.cpu.dcache.overall_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency 232system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 233system.cpu.icache.tags.replacements 184976 # number of replacements 234system.cpu.icache.tags.tagsinuse 2004.091327 # Cycle average of tags in use 235system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. 236system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 237system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. 238system.cpu.icache.tags.warmup_cycle 144688165500 # Cycle when the warmup percentage was hit. 239system.cpu.icache.tags.occ_blocks::cpu.inst 2004.091327 # Average occupied blocks per requestor 240system.cpu.icache.tags.occ_percent::cpu.inst 0.978560 # Average percentage of cache occupancy 241system.cpu.icache.tags.occ_percent::total 0.978560 # Average percentage of cache occupancy 242system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 243system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 244system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 245system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 246system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 247system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 248system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 249system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses 250system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses 251system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 252system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits 253system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits 254system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits 255system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits 256system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits 257system.cpu.icache.overall_hits::total 134366557 # number of overall hits 258system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 259system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 260system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 261system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 262system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 263system.cpu.icache.overall_misses::total 187024 # number of overall misses 264system.cpu.icache.ReadReq_miss_latency::cpu.inst 2844752500 # number of ReadReq miss cycles 265system.cpu.icache.ReadReq_miss_latency::total 2844752500 # number of ReadReq miss cycles 266system.cpu.icache.demand_miss_latency::cpu.inst 2844752500 # number of demand (read+write) miss cycles 267system.cpu.icache.demand_miss_latency::total 2844752500 # number of demand (read+write) miss cycles 268system.cpu.icache.overall_miss_latency::cpu.inst 2844752500 # number of overall miss cycles 269system.cpu.icache.overall_miss_latency::total 2844752500 # number of overall miss cycles 270system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) 271system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) 272system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses 273system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses 274system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses 275system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses 276system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 277system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 278system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 279system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 280system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 281system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses 282system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15210.628048 # average ReadReq miss latency 283system.cpu.icache.ReadReq_avg_miss_latency::total 15210.628048 # average ReadReq miss latency 284system.cpu.icache.demand_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency 285system.cpu.icache.demand_avg_miss_latency::total 15210.628048 # average overall miss latency 286system.cpu.icache.overall_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency 287system.cpu.icache.overall_avg_miss_latency::total 15210.628048 # average overall miss latency 288system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 290system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 291system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 292system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 293system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 294system.cpu.icache.writebacks::writebacks 184976 # number of writebacks 295system.cpu.icache.writebacks::total 184976 # number of writebacks 296system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 297system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 298system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 299system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 300system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 301system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses 302system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2657728500 # number of ReadReq MSHR miss cycles 303system.cpu.icache.ReadReq_mshr_miss_latency::total 2657728500 # number of ReadReq MSHR miss cycles 304system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2657728500 # number of demand (read+write) MSHR miss cycles 305system.cpu.icache.demand_mshr_miss_latency::total 2657728500 # number of demand (read+write) MSHR miss cycles 306system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2657728500 # number of overall MSHR miss cycles 307system.cpu.icache.overall_mshr_miss_latency::total 2657728500 # number of overall MSHR miss cycles 308system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses 309system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses 310system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses 311system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses 312system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses 313system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses 314system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14210.628048 # average ReadReq mshr miss latency 315system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14210.628048 # average ReadReq mshr miss latency 316system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency 317system.cpu.icache.demand_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency 318system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency 319system.cpu.icache.overall_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency 320system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 321system.cpu.l2cache.tags.replacements 99926 # number of replacements 322system.cpu.l2cache.tags.tagsinuse 32138.485238 # Cycle average of tags in use 323system.cpu.l2cache.tags.total_refs 536406 # Total number of references to valid blocks. 324system.cpu.l2cache.tags.sampled_refs 132694 # Sample count of references to valid blocks. 325system.cpu.l2cache.tags.avg_refs 4.042428 # Average number of references to valid blocks. 326system.cpu.l2cache.tags.warmup_cycle 26729442000 # Cycle when the warmup percentage was hit. 327system.cpu.l2cache.tags.occ_blocks::writebacks 711.528666 # Average occupied blocks per requestor 328system.cpu.l2cache.tags.occ_blocks::cpu.inst 3108.349977 # Average occupied blocks per requestor 329system.cpu.l2cache.tags.occ_blocks::cpu.data 28318.606595 # Average occupied blocks per requestor 330system.cpu.l2cache.tags.occ_percent::writebacks 0.021714 # Average percentage of cache occupancy 331system.cpu.l2cache.tags.occ_percent::cpu.inst 0.094859 # Average percentage of cache occupancy 332system.cpu.l2cache.tags.occ_percent::cpu.data 0.864215 # Average percentage of cache occupancy 333system.cpu.l2cache.tags.occ_percent::total 0.980789 # Average percentage of cache occupancy 334system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 335system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id 336system.cpu.l2cache.tags.age_task_id_blocks_1024::1 570 # Occupied blocks per task id 337system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10913 # Occupied blocks per task id 338system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20279 # Occupied blocks per task id 339system.cpu.l2cache.tags.age_task_id_blocks_1024::4 818 # Occupied blocks per task id 340system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 341system.cpu.l2cache.tags.tag_accesses 5486262 # Number of tag accesses 342system.cpu.l2cache.tags.data_accesses 5486262 # Number of data accesses 343system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 344system.cpu.l2cache.WritebackDirty_hits::writebacks 123615 # number of WritebackDirty hits 345system.cpu.l2cache.WritebackDirty_hits::total 123615 # number of WritebackDirty hits 346system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits 347system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits 348system.cpu.l2cache.ReadExReq_hits::cpu.data 3868 # number of ReadExReq hits 349system.cpu.l2cache.ReadExReq_hits::total 3868 # number of ReadExReq hits 350system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178794 # number of ReadCleanReq hits 351system.cpu.l2cache.ReadCleanReq_hits::total 178794 # number of ReadCleanReq hits 352system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24230 # number of ReadSharedReq hits 353system.cpu.l2cache.ReadSharedReq_hits::total 24230 # number of ReadSharedReq hits 354system.cpu.l2cache.demand_hits::cpu.inst 178794 # number of demand (read+write) hits 355system.cpu.l2cache.demand_hits::cpu.data 28098 # number of demand (read+write) hits 356system.cpu.l2cache.demand_hits::total 206892 # number of demand (read+write) hits 357system.cpu.l2cache.overall_hits::cpu.inst 178794 # number of overall hits 358system.cpu.l2cache.overall_hits::cpu.data 28098 # number of overall hits 359system.cpu.l2cache.overall_hits::total 206892 # number of overall hits 360system.cpu.l2cache.ReadExReq_misses::cpu.data 101311 # number of ReadExReq misses 361system.cpu.l2cache.ReadExReq_misses::total 101311 # number of ReadExReq misses 362system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8230 # number of ReadCleanReq misses 363system.cpu.l2cache.ReadCleanReq_misses::total 8230 # number of ReadCleanReq misses 364system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21270 # number of ReadSharedReq misses 365system.cpu.l2cache.ReadSharedReq_misses::total 21270 # number of ReadSharedReq misses 366system.cpu.l2cache.demand_misses::cpu.inst 8230 # number of demand (read+write) misses 367system.cpu.l2cache.demand_misses::cpu.data 122581 # number of demand (read+write) misses 368system.cpu.l2cache.demand_misses::total 130811 # number of demand (read+write) misses 369system.cpu.l2cache.overall_misses::cpu.inst 8230 # number of overall misses 370system.cpu.l2cache.overall_misses::cpu.data 122581 # number of overall misses 371system.cpu.l2cache.overall_misses::total 130811 # number of overall misses 372system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6130000500 # number of ReadExReq miss cycles 373system.cpu.l2cache.ReadExReq_miss_latency::total 6130000500 # number of ReadExReq miss cycles 374system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 498248500 # number of ReadCleanReq miss cycles 375system.cpu.l2cache.ReadCleanReq_miss_latency::total 498248500 # number of ReadCleanReq miss cycles 376system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1286927500 # number of ReadSharedReq miss cycles 377system.cpu.l2cache.ReadSharedReq_miss_latency::total 1286927500 # number of ReadSharedReq miss cycles 378system.cpu.l2cache.demand_miss_latency::cpu.inst 498248500 # number of demand (read+write) miss cycles 379system.cpu.l2cache.demand_miss_latency::cpu.data 7416928000 # number of demand (read+write) miss cycles 380system.cpu.l2cache.demand_miss_latency::total 7915176500 # number of demand (read+write) miss cycles 381system.cpu.l2cache.overall_miss_latency::cpu.inst 498248500 # number of overall miss cycles 382system.cpu.l2cache.overall_miss_latency::cpu.data 7416928000 # number of overall miss cycles 383system.cpu.l2cache.overall_miss_latency::total 7915176500 # number of overall miss cycles 384system.cpu.l2cache.WritebackDirty_accesses::writebacks 123615 # number of WritebackDirty accesses(hits+misses) 385system.cpu.l2cache.WritebackDirty_accesses::total 123615 # number of WritebackDirty accesses(hits+misses) 386system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) 387system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) 388system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) 389system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) 390system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) 391system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) 392system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) 393system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) 394system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses 395system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses 396system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses 397system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses 398system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses 399system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses 400system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963225 # miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_miss_rate::total 0.963225 # miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.044005 # miss rate for ReadCleanReq accesses 403system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.044005 # miss rate for ReadCleanReq accesses 404system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.467473 # miss rate for ReadSharedReq accesses 405system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.467473 # miss rate for ReadSharedReq accesses 406system.cpu.l2cache.demand_miss_rate::cpu.inst 0.044005 # miss rate for demand accesses 407system.cpu.l2cache.demand_miss_rate::cpu.data 0.813524 # miss rate for demand accesses 408system.cpu.l2cache.demand_miss_rate::total 0.387355 # miss rate for demand accesses 409system.cpu.l2cache.overall_miss_rate::cpu.inst 0.044005 # miss rate for overall accesses 410system.cpu.l2cache.overall_miss_rate::cpu.data 0.813524 # miss rate for overall accesses 411system.cpu.l2cache.overall_miss_rate::total 0.387355 # miss rate for overall accesses 412system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60506.761359 # average ReadExReq miss latency 413system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60506.761359 # average ReadExReq miss latency 414system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60540.522479 # average ReadCleanReq miss latency 415system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60540.522479 # average ReadCleanReq miss latency 416system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60504.348848 # average ReadSharedReq miss latency 417system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60504.348848 # average ReadSharedReq miss latency 418system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency 419system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency 420system.cpu.l2cache.demand_avg_miss_latency::total 60508.493170 # average overall miss latency 421system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency 422system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency 423system.cpu.l2cache.overall_avg_miss_latency::total 60508.493170 # average overall miss latency 424system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu.l2cache.writebacks::writebacks 85566 # number of writebacks 431system.cpu.l2cache.writebacks::total 85566 # number of writebacks 432system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 433system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 434system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101311 # number of ReadExReq MSHR misses 435system.cpu.l2cache.ReadExReq_mshr_misses::total 101311 # number of ReadExReq MSHR misses 436system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8230 # number of ReadCleanReq MSHR misses 437system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8230 # number of ReadCleanReq MSHR misses 438system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21270 # number of ReadSharedReq MSHR misses 439system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21270 # number of ReadSharedReq MSHR misses 440system.cpu.l2cache.demand_mshr_misses::cpu.inst 8230 # number of demand (read+write) MSHR misses 441system.cpu.l2cache.demand_mshr_misses::cpu.data 122581 # number of demand (read+write) MSHR misses 442system.cpu.l2cache.demand_mshr_misses::total 130811 # number of demand (read+write) MSHR misses 443system.cpu.l2cache.overall_mshr_misses::cpu.inst 8230 # number of overall MSHR misses 444system.cpu.l2cache.overall_mshr_misses::cpu.data 122581 # number of overall MSHR misses 445system.cpu.l2cache.overall_mshr_misses::total 130811 # number of overall MSHR misses 446system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5116890500 # number of ReadExReq MSHR miss cycles 447system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5116890500 # number of ReadExReq MSHR miss cycles 448system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 415948500 # number of ReadCleanReq MSHR miss cycles 449system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 415948500 # number of ReadCleanReq MSHR miss cycles 450system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1074227500 # number of ReadSharedReq MSHR miss cycles 451system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1074227500 # number of ReadSharedReq MSHR miss cycles 452system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 415948500 # number of demand (read+write) MSHR miss cycles 453system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6191118000 # number of demand (read+write) MSHR miss cycles 454system.cpu.l2cache.demand_mshr_miss_latency::total 6607066500 # number of demand (read+write) MSHR miss cycles 455system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 415948500 # number of overall MSHR miss cycles 456system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6191118000 # number of overall MSHR miss cycles 457system.cpu.l2cache.overall_mshr_miss_latency::total 6607066500 # number of overall MSHR miss cycles 458system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 459system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 460system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963225 # mshr miss rate for ReadExReq accesses 461system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963225 # mshr miss rate for ReadExReq accesses 462system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for ReadCleanReq accesses 463system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044005 # mshr miss rate for ReadCleanReq accesses 464system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.467473 # mshr miss rate for ReadSharedReq accesses 465system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.467473 # mshr miss rate for ReadSharedReq accesses 466system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for demand accesses 467system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for demand accesses 468system.cpu.l2cache.demand_mshr_miss_rate::total 0.387355 # mshr miss rate for demand accesses 469system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for overall accesses 470system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for overall accesses 471system.cpu.l2cache.overall_mshr_miss_rate::total 0.387355 # mshr miss rate for overall accesses 472system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50506.761359 # average ReadExReq mshr miss latency 473system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50506.761359 # average ReadExReq mshr miss latency 474system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479 # average ReadCleanReq mshr miss latency 475system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479 # average ReadCleanReq mshr miss latency 476system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848 # average ReadSharedReq mshr miss latency 477system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848 # average ReadSharedReq mshr miss latency 478system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency 479system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency 480system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency 481system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency 482system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency 483system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency 484system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. 485system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 486system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 487system.cpu.toL2Bus.snoop_filter.tot_snoops 3837 # Total number of snoops made to the snoop filter. 488system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 489system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 490system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 491system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution 492system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::CleanEvict 37328 # Transaction distribution 495system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution 497system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution 498system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution 499system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) 501system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) 502system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) 503system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 # Cumulative packet size per connected master and slave (bytes) 504system.cpu.toL2Bus.pkt_size::total 41362816 # Cumulative packet size per connected master and slave (bytes) 505system.cpu.toL2Bus.snoops 99926 # Total snoops (count) 506system.cpu.toL2Bus.snoopTraffic 5476224 # Total snoop traffic (bytes) 507system.cpu.toL2Bus.snoop_fanout::samples 437629 # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::mean 0.008919 # Request fanout histogram 509system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% # Request fanout histogram 513system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 514system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 515system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 516system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 517system.cpu.toL2Bus.snoop_fanout::total 437629 # Request fanout histogram 518system.cpu.toL2Bus.reqLayer0.occupancy 643222000 # Layer occupancy (ticks) 519system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 520system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) 521system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 522system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) 523system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 524system.membus.snoop_filter.tot_requests 226995 # Total number of requests made to the snoop filter. 525system.membus.snoop_filter.hit_single_requests 96184 # Number of requests hitting in the snoop filter with a single holder of the requested data. 526system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 527system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 528system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 529system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 530system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states 531system.membus.trans_dist::ReadResp 29500 # Transaction distribution 532system.membus.trans_dist::WritebackDirty 85566 # Transaction distribution 533system.membus.trans_dist::CleanEvict 10618 # Transaction distribution 534system.membus.trans_dist::ReadExReq 101311 # Transaction distribution 535system.membus.trans_dist::ReadExResp 101311 # Transaction distribution 536system.membus.trans_dist::ReadSharedReq 29500 # Transaction distribution 537system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 # Packet count per connected master and slave (bytes) 538system.membus.pkt_count::total 357806 # Packet count per connected master and slave (bytes) 539system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 # Cumulative packet size per connected master and slave (bytes) 540system.membus.pkt_size::total 13848128 # Cumulative packet size per connected master and slave (bytes) 541system.membus.snoops 0 # Total snoops (count) 542system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 543system.membus.snoop_fanout::samples 130811 # Request fanout histogram 544system.membus.snoop_fanout::mean 0 # Request fanout histogram 545system.membus.snoop_fanout::stdev 0 # Request fanout histogram 546system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 547system.membus.snoop_fanout::0 130811 100.00% 100.00% # Request fanout histogram 548system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 549system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 550system.membus.snoop_fanout::min_value 0 # Request fanout histogram 551system.membus.snoop_fanout::max_value 0 # Request fanout histogram 552system.membus.snoop_fanout::total 130811 # Request fanout histogram 553system.membus.reqLayer0.occupancy 570211500 # Layer occupancy (ticks) 554system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 555system.membus.respLayer1.occupancy 654055000 # Layer occupancy (ticks) 556system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 557 558---------- End Simulation Statistics ----------