Cross Reference: /gem5/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt

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stats.txt (10892:bd37e25fb3b7)	stats.txt (11138:a611a23c8cc2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.202233 # Number of seconds simulated	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.202233 # Number of seconds simulated
4sim_ticks 202232894500 # Number of ticks simulated 5final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)	4sim_ticks 202232960500 # Number of ticks simulated 5final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks	6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1204132 # Simulator instruction rate (inst/s) 8host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1811881435 # Simulator tick rate (ticks/s) 10host_mem_usage 302340 # Number of bytes of host memory used 11host_seconds 111.61 # Real time elapsed on the host	7host_inst_rate 1135828 # Simulator instruction rate (inst/s) 8host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1709104516 # Simulator tick rate (ticks/s) 10host_mem_usage 304720 # Number of bytes of host memory used 11host_seconds 118.33 # Real time elapsed on the host
12sim_insts 134398962 # Number of instructions simulated 13sim_ops 136139190 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 575680 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7827008 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8402688 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 575680 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 575680 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5453120 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5453120 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 8995 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 122297 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory	12sim_insts 134398962 # Number of instructions simulated 13sim_ops 136139190 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 575680 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7827008 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8402688 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 575680 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 575680 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5453120 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5453120 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 8995 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 122297 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s)	28system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s)
39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.workload.num_syscalls 1946 # Number of system calls	39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.workload.num_syscalls 1946 # Number of system calls
41system.cpu.numCycles 404465789 # number of cpu cycles simulated	41system.cpu.numCycles 404465921 # number of cpu cycles simulated
42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 134398962 # Number of instructions committed 45system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses 48system.cpu.num_func_calls 1709332 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls 50system.cpu.num_int_insts 115187746 # number of integer instructions 51system.cpu.num_fp_insts 2326977 # number of float instructions 52system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read 53system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written 54system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 56system.cpu.num_mem_refs 58160248 # number of memory refs 57system.cpu.num_load_insts 37275867 # Number of load instructions 58system.cpu.num_store_insts 20884381 # Number of store instructions 59system.cpu.num_idle_cycles 0.002000 # Number of idle cycles	42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 134398962 # Number of instructions committed 45system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses 48system.cpu.num_func_calls 1709332 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls 50system.cpu.num_int_insts 115187746 # number of integer instructions 51system.cpu.num_fp_insts 2326977 # number of float instructions 52system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read 53system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written 54system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written 56system.cpu.num_mem_refs 58160248 # number of memory refs 57system.cpu.num_load_insts 37275867 # Number of load instructions 58system.cpu.num_store_insts 20884381 # Number of store instructions 59system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
60system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles	60system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles
61system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 62system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 63system.cpu.Branches 12719095 # Number of branches fetched 64system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 65system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction 66system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 67system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 68system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction 69system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction 70system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction 71system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction 72system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction 73system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction 74system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction 75system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction 76system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction 77system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction 78system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction 79system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction 80system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction 81system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction 82system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction 83system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction 84system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction 85system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction 86system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction 87system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction 88system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction 89system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction 90system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction 91system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 92system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 93system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 94system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction 95system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 136293798 # Class of executed instruction 99system.cpu.dcache.tags.replacements 146582 # number of replacements	61system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 62system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 63system.cpu.Branches 12719095 # Number of branches fetched 64system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction 65system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction 66system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction 67system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction 68system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction 69system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction 70system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction 71system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction 72system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction 73system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction 74system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction 75system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction 76system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction 77system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction 78system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction 79system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction 80system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction 81system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction 82system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction 83system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction 84system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction 85system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction 86system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction 87system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction 88system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction 89system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction 90system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction 91system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction 92system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction 93system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction 94system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction 95system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 136293798 # Class of executed instruction 99system.cpu.dcache.tags.replacements 146582 # number of replacements
100system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use	100system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use
101system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. 102system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. 103system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.	101system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. 102system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. 103system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
104system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit. 105system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor	104system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit. 105system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor
106system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy 107system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::2 3529 # Occupied blocks per task id 112system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 113system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses 114system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses 115system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits 123system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits 124system.cpu.dcache.overall_hits::total 57944941 # number of overall hits 125system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses 126system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses 127system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 128system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 129system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 130system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 131system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses 134system.cpu.dcache.overall_misses::total 150663 # number of overall misses	106system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy 107system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::2 3529 # Occupied blocks per task id 112system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 113system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses 114system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses 115system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits 116system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits 117system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits 119system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits 120system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits 121system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits 123system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits 124system.cpu.dcache.overall_hits::total 57944941 # number of overall hits 125system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses 126system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses 127system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses 128system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses 129system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses 130system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses 131system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses 134system.cpu.dcache.overall_misses::total 150663 # number of overall misses
135system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles	135system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles
137system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles 139system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles 140system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles	137system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles 139system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles 140system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
141system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles	141system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles 142system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles 143system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles 144system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles
145system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 150system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 151system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 152system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses 153system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses 154system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses 155system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses 156system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses 157system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 158system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 159system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 160system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses	145system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) 150system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) 151system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses 152system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses 153system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses 154system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses 155system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses 156system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses 157system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses 158system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses 159system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses 160system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency	165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency
167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency 170system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency	167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency 169system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency 170system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
171system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency 172system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency	171system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency 172system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency
175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.cpu.dcache.fast_writes 0 # number of fast writes performed 182system.cpu.dcache.cache_copies 0 # number of cache copies performed 183system.cpu.dcache.writebacks::writebacks 123896 # number of writebacks 184system.cpu.dcache.writebacks::total 123896 # number of writebacks 185system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses 186system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses 187system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 189system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 190system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 191system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses 192system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses 193system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses 194system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses	175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.cpu.dcache.fast_writes 0 # number of fast writes performed 182system.cpu.dcache.cache_copies 0 # number of cache copies performed 183system.cpu.dcache.writebacks::writebacks 123896 # number of writebacks 184system.cpu.dcache.writebacks::total 123896 # number of writebacks 185system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses 186system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses 187system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses 189system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses 190system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses 191system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses 192system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses 193system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses 194system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
195system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles 196system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles	195system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles 196system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles
197system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles 200system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles	197system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles 200system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles
201system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles 204system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles	201system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles 204system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles
205system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 209system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 210system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 211system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 212system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 213system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 214system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses	205system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses 209system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses 210system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses 211system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses 212system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses 213system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses 214system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
215system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency 216system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency	215system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency 216system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency
217system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency 218system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency 219system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency 220system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency	217system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency 218system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency 219system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency 220system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency
221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency 223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency	221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency 223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
225system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 226system.cpu.icache.tags.replacements 184976 # number of replacements	225system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 226system.cpu.icache.tags.replacements 184976 # number of replacements
227system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use	227system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use
228system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. 229system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 230system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.	228system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. 229system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. 230system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
231system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit. 232system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor	231system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit. 232system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor
233system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy 234system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy 235system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 241system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 242system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses 243system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses 244system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits 245system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits 246system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits 247system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits 248system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits 249system.cpu.icache.overall_hits::total 134366547 # number of overall hits 250system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 251system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 252system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 253system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 254system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 255system.cpu.icache.overall_misses::total 187024 # number of overall misses	233system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy 234system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy 235system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 237system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id 241system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 242system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses 243system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses 244system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits 245system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits 246system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits 247system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits 248system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits 249system.cpu.icache.overall_hits::total 134366547 # number of overall hits 250system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses 251system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses 252system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses 253system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses 254system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses 255system.cpu.icache.overall_misses::total 187024 # number of overall misses
256system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles 257system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles 258system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles 259system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles 260system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles 261system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles	256system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles 257system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles 258system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles 259system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles 260system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles 261system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles
262system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses 265system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses 266system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses 267system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses 268system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 269system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 270system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 271system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 272system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 273system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses	262system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses 265system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses 266system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses 267system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses 268system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses 269system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses 270system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses 271system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses 272system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses 273system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
274system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency 275system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency 276system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency 277system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency 279system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency	274system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency 275system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency 276system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency 277system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency 279system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency
280system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 281system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 283system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 284system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 285system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 286system.cpu.icache.fast_writes 0 # number of fast writes performed 287system.cpu.icache.cache_copies 0 # number of cache copies performed 288system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 289system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 290system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 291system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 292system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 293system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses	280system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 281system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 283system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 284system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 285system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 286system.cpu.icache.fast_writes 0 # number of fast writes performed 287system.cpu.icache.cache_copies 0 # number of cache copies performed 288system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses 289system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses 290system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses 291system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses 292system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses 293system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
294system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles 295system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles 298system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles	294system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles 295system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles 298system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles