| stats.txt (11687:b3d5f0e9e258) | stats.txt (11731:c473ca7cc650) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.128202 # Number of seconds simulated 4sim_ticks 128202163500 # Number of ticks simulated 5final_tick 128202163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.128204 # Number of seconds simulated 4sim_ticks 128204299500 # Number of ticks simulated 5final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1220543 # Simulator instruction rate (inst/s) 8host_op_rate 1558290 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2223504943 # Simulator tick rate (ticks/s) 10host_mem_usage 279580 # Number of bytes of host memory used 11host_seconds 57.66 # Real time elapsed on the host | 7host_inst_rate 442445 # Simulator instruction rate (inst/s) 8host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 806030069 # Simulator tick rate (ticks/s) 10host_mem_usage 262052 # Number of bytes of host memory used 11host_seconds 159.06 # Real time elapsed on the host |
| 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory |
| 29system.physmem.bw_read::cpu.inst 1820125 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 61927192 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 63747317 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1820125 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1820125 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 43170317 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 43170317 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 43170317 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1820125 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 61927192 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 106917634 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 29system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 41system.cpu_clk_domain.clock 500 # Clock period in ticks | 41system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses | 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses |
| 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses 162system.cpu.workload.num_syscalls 1946 # Number of system calls | 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses 162system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 163system.cpu.pwrStateResidencyTicks::ON 128202163500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 256404327 # number of cpu cycles simulated | 163system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 256408599 # number of cpu cycles simulated |
| 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 70373651 # Number of instructions committed 168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 171system.cpu.num_func_calls 3311620 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 177system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written 181system.cpu.num_mem_refs 43422001 # number of memory refs 182system.cpu.num_load_insts 22866262 # Number of load instructions 183system.cpu.num_store_insts 20555739 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 70373651 # Number of instructions committed 168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 171system.cpu.num_func_calls 3311620 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 177system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written 181system.cpu.num_mem_refs 43422001 # number of memory refs 182system.cpu.num_load_insts 22866262 # Number of load instructions 183system.cpu.num_store_insts 20555739 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 185system.cpu.num_busy_cycles 256404326.998000 # Number of busy cycles | 185system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles |
| 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 13741468 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction 191system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction --- 26 unchanged lines hidden (view full) --- 220system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 221system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction 222system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction 223system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction 224system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction 225system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 227system.cpu.op_class::total 90690106 # Class of executed instruction | 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 13741468 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction 191system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction --- 26 unchanged lines hidden (view full) --- 220system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 221system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction 222system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction 223system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction 224system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction 225system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 227system.cpu.op_class::total 90690106 # Class of executed instruction |
| 228system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 228system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 229system.cpu.dcache.tags.replacements 155902 # number of replacements | 229system.cpu.dcache.tags.replacements 155902 # number of replacements |
| 230system.cpu.dcache.tags.tagsinuse 4075.863858 # Cycle average of tags in use | 230system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use |
| 231system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. 232system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 233system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. 234system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. | 231system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. 232system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 233system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. 234system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. |
| 235system.cpu.dcache.tags.occ_blocks::cpu.data 4075.863858 # Average occupied blocks per requestor | 235system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor |
| 236system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy 237system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy 238system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 240system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id 241system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id 242system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 243system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 244system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses | 236system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy 237system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy 238system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 240system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id 241system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id 242system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 243system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 244system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses |
| 245system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 245system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 246system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits 247system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits 248system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 249system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 250system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits 251system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits 252system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 253system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 356system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency 357system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency 358system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency 359system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency 360system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency 361system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency 362system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency 363system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency | 246system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits 247system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits 248system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 249system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 250system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits 251system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits 252system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 253system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 356system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency 357system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency 358system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency 359system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency 360system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency 361system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency 362system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency 363system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency |
| 364system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 364system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 365system.cpu.icache.tags.replacements 16890 # number of replacements | 365system.cpu.icache.tags.replacements 16890 # number of replacements |
| 366system.cpu.icache.tags.tagsinuse 1732.172375 # Cycle average of tags in use | 366system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use |
| 367system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 368system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 369system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 370system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 367system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 368system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 369system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 370system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 371system.cpu.icache.tags.occ_blocks::cpu.inst 1732.172375 # Average occupied blocks per requestor 372system.cpu.icache.tags.occ_percent::cpu.inst 0.845787 # Average percentage of cache occupancy 373system.cpu.icache.tags.occ_percent::total 0.845787 # Average percentage of cache occupancy | 371system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor 372system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy 373system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy |
| 374system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 375system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 376system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 379system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 380system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses | 374system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 375system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 376system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 379system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 380system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses |
| 382system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 382system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 383system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 384system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 385system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 386system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 387system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 388system.cpu.icache.overall_hits::total 78126184 # number of overall hits 389system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 390system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 443system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 444system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 445system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency 446system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency 447system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency 449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 450system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency | 383system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 384system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 385system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 386system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 387system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 388system.cpu.icache.overall_hits::total 78126184 # number of overall hits 389system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 390system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 443system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 444system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 445system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency 446system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency 447system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency 449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 450system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency |
| 451system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 451system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 452system.cpu.l2cache.tags.replacements 96062 # number of replacements | 452system.cpu.l2cache.tags.replacements 96062 # number of replacements |
| 453system.cpu.l2cache.tags.tagsinuse 31698.820174 # Cycle average of tags in use | 453system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use |
| 454system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. 455system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. 456system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. | 454system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. 455system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. 456system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. |
| 457system.cpu.l2cache.tags.warmup_cycle 20553705000 # Cycle when the warmup percentage was hit. 458system.cpu.l2cache.tags.occ_blocks::writebacks 380.243921 # Average occupied blocks per requestor 459system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373654 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.202598 # Average occupied blocks per requestor | 457system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. 458system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor 459system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor |
| 461system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses | 461system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses |
| 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 475system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits 476system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits 477system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 478system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 479system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits 480system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits 481system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits 482system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 613system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency 614system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency 615system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 616system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 617system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 618system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. 619system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 620system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 475system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits 476system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits 477system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 478system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 479system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits 480system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits 481system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits 482system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 613system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency 614system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency 615system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 616system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 617system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 618system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. 619system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 620system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 621system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 621system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 622system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 628system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 629system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 653system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 654system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 655system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. 656system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. 657system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 658system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 659system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 660system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 622system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 628system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 629system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 653system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 654system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 655system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. 656system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. 657system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 658system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 659system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 660system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 661system.membus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states | 661system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states |
| 662system.membus.trans_dist::ReadResp 25376 # Transaction distribution 663system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution 664system.membus.trans_dist::CleanEvict 6466 # Transaction distribution 665system.membus.trans_dist::ReadExReq 102320 # Transaction distribution 666system.membus.trans_dist::ReadExResp 102320 # Transaction distribution 667system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution 668system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 662system.membus.trans_dist::ReadResp 25376 # Transaction distribution 663system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution 664system.membus.trans_dist::CleanEvict 6466 # Transaction distribution 665system.membus.trans_dist::ReadExReq 102320 # Transaction distribution 666system.membus.trans_dist::ReadExResp 102320 # Transaction distribution 667system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution 668system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- |