Cross Reference: /gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt

stats.txt (11515:c48c7cc5a522)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated 4sim_ticks 128076834500 # Number of ticks simulated 5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated 4sim_ticks 128076834500 # Number of ticks simulated 5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1113892 # Simulator instruction rate (inst/s) 8host_op_rate 1422128 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2027232976 # Simulator tick rate (ticks/s) 10host_mem_usage 319564 # Number of bytes of host memory used 11host_seconds 63.18 # Real time elapsed on the host	7host_inst_rate 1093594 # Simulator instruction rate (inst/s) 8host_op_rate 1396212 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1990290276 # Simulator tick rate (ticks/s) 10host_mem_usage 320240 # Number of bytes of host memory used 11host_seconds 64.35 # Real time elapsed on the host
12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 32system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)
	40system.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
39system.cpu_clk_domain.clock 500 # Clock period in ticks	41system.cpu_clk_domain.clock 500 # Clock period in ticks
	42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses	73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses
	102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 1946 # Number of system calls	133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses 162system.cpu.workload.num_syscalls 1946 # Number of system calls
	163system.cpu.pwrStateResidencyTicks::ON 128076834500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 256153669 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 70373651 # Number of instructions committed 161system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 164system.cpu.num_func_calls 3311620 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 90690106 # Class of executed instruction	164system.cpu.numCycles 256153669 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 70373651 # Number of instructions committed 168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 171system.cpu.num_func_calls 3311620 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 216system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 217system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 218system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 219system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 220system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 221system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 222system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 223system.cpu.op_class::total 90690106 # Class of executed instruction
	224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
217system.cpu.dcache.tags.replacements 155902 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id 230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 232system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses	225system.cpu.dcache.tags.replacements 155902 # number of replacements 226system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use 227system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. 228system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 229system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. 230system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. 231system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor 232system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy 233system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy 234system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 235system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 236system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id 237system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id 238system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 239system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 240system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
	241system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
233system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits 234system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits 235system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 236system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 237system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits 238system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits 239system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 240system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency 344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency 345system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 346system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 348system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 350system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency	242system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits 243system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits 244system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 245system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 246system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits 247system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits 248system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 249system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits --- 102 unchanged lines hidden (view full) --- 352system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency 353system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency 354system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 355system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 356system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 357system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 358system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 359system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency
	360system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
351system.cpu.icache.tags.replacements 16890 # number of replacements 352system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use 353system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 354system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 355system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 356system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 357system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor 358system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy 359system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy 360system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 367system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses	361system.cpu.icache.tags.replacements 16890 # number of replacements 362system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use 363system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 364system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 365system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 366system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 367system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor 368system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy 369system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy 370system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 371system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 372system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 373system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 374system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 375system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 376system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 377system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses
	378system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
368system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 369system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 370system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 371system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 372system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 373system.cpu.icache.overall_hits::total 78126184 # number of overall hits 374system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 375system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 429system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency	379system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 380system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 381system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 382system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 383system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 384system.cpu.icache.overall_hits::total 78126184 # number of overall hits 385system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 386system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 439system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 440system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 441system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 442system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 443system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 444system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 445system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 446system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
	447system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
436system.cpu.l2cache.tags.replacements 95333 # number of replacements 437system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use 438system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses	448system.cpu.l2cache.tags.replacements 95333 # number of replacements 449system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use 450system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. 451system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. 452system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. 453system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 454system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor 455system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 462system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 463system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id 464system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id 465system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id 467system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id 468system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses 469system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses
	470system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
458system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits 459system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits 460system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 461system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 462system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits 463system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits 464system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits 465system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 597system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency 598system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. 602system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 603system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	471system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits 472system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits 473system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 474system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 475system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits 476system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits 477system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits 478system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 610system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency 611system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 612system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 613system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 614system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. 615system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 616system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	617system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
604system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 628system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram 630system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) 631system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 632system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 633system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 634system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 635system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)	618system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 619system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution 620system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 621system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 642system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 643system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram 644system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) 645system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 646system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 647system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 648system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 649system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
	650system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
636system.membus.trans_dist::ReadResp 25194 # Transaction distribution 637system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution 638system.membus.trans_dist::CleanEvict 6168 # Transaction distribution 639system.membus.trans_dist::ReadExReq 102281 # Transaction distribution 640system.membus.trans_dist::ReadExResp 102281 # Transaction distribution 641system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution 642system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) 643system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---	651system.membus.trans_dist::ReadResp 25194 # Transaction distribution 652system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution 653system.membus.trans_dist::CleanEvict 6168 # Transaction distribution 654system.membus.trans_dist::ReadExReq 102281 # Transaction distribution 655system.membus.trans_dist::ReadExResp 102281 # Transaction distribution 656system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution 657system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) 658system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.128077 # Number of seconds simulated
4sim_ticks 128076834500 # Number of ticks simulated
5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1113892 # Simulator instruction rate (inst/s)
8host_op_rate 1422128 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2027232976 # Simulator tick rate (ticks/s)
10host_mem_usage 319564 # Number of bytes of host memory used
11host_seconds 63.18 # Real time elapsed on the host

7host_inst_rate 1093594 # Simulator instruction rate (inst/s)
8host_op_rate 1396212 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1990290276 # Simulator tick rate (ticks/s)
10host_mem_usage 320240 # Number of bytes of host memory used
11host_seconds 64.35 # Real time elapsed on the host

12sim_insts 70373651 # Number of instructions simulated
13sim_ops 89847385 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory
22system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory

--- 7 unchanged lines hidden (view full) ---

31system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory
19system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory
23system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory

--- 7 unchanged lines hidden (view full) ---

32system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)

40system.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

39system.cpu_clk_domain.clock 500 # Clock period in ticks

41system.cpu_clk_domain.clock 500 # Clock period in ticks

42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

69system.cpu.dtb.walker.walks 0 # Table walker walks requested
70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses

73system.cpu.dtb.walker.walks 0 # Table walker walks requested
74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
96system.cpu.dtb.read_accesses 0 # DTB read accesses
97system.cpu.dtb.write_accesses 0 # DTB write accesses
98system.cpu.dtb.inst_accesses 0 # ITB inst accesses
99system.cpu.dtb.hits 0 # DTB hits
100system.cpu.dtb.misses 0 # DTB misses
101system.cpu.dtb.accesses 0 # DTB accesses

102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

127system.cpu.itb.walker.walks 0 # Table walker walks requested
128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 1946 # Number of system calls

133system.cpu.itb.walker.walks 0 # Table walker walks requested
134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
156system.cpu.itb.read_accesses 0 # DTB read accesses
157system.cpu.itb.write_accesses 0 # DTB write accesses
158system.cpu.itb.inst_accesses 0 # ITB inst accesses
159system.cpu.itb.hits 0 # DTB hits
160system.cpu.itb.misses 0 # DTB misses
161system.cpu.itb.accesses 0 # DTB accesses
162system.cpu.workload.num_syscalls 1946 # Number of system calls

163system.cpu.pwrStateResidencyTicks::ON 128076834500 # Cumulative time (in ticks) in various power states

157system.cpu.numCycles 256153669 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 70373651 # Number of instructions committed
161system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
164system.cpu.num_func_calls 3311620 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 90690106 # Class of executed instruction

164system.cpu.numCycles 256153669 # number of cpu cycles simulated
165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
167system.cpu.committedInsts 70373651 # Number of instructions committed
168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed
169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
171system.cpu.num_func_calls 3311620 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

216system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
217system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
218system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
219system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
220system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
221system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
222system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
223system.cpu.op_class::total 90690106 # Class of executed instruction

224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

217system.cpu.dcache.tags.replacements 155902 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks.
222system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor
224system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id
230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
232system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses

225system.cpu.dcache.tags.replacements 155902 # number of replacements
226system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
227system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
228system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
229system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks.
230system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
231system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor
232system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy
233system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy
234system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
235system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
236system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id
237system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id
238system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
239system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
240system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses

241system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

233system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits
234system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits
235system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
236system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
237system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits
238system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits
239system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
240system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits

--- 102 unchanged lines hidden (view full) ---

343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency
344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency
345system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency
346system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency
347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency
348system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency
349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency
350system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency

242system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits
243system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits
244system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
245system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
246system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits
247system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits
248system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
249system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits

--- 102 unchanged lines hidden (view full) ---

352system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency
353system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency
354system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency
355system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency
356system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency
357system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency
358system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency
359system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency

360system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

351system.cpu.icache.tags.replacements 16890 # number of replacements
352system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use
353system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks.
354system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
355system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks.
356system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
357system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor
358system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy
359system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy
360system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
362system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
363system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
364system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
365system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
366system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses
367system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses

361system.cpu.icache.tags.replacements 16890 # number of replacements
362system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use
363system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks.
364system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
365system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks.
366system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
367system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor
368system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy
369system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy
370system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
371system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
372system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
373system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
374system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
375system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
376system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses
377system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses

378system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

368system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits
369system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits
370system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits
371system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits
372system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits
373system.cpu.icache.overall_hits::total 78126184 # number of overall hits
374system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
375system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
429system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency
431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency
432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
433system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
435system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency

379system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits
380system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits
381system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits
382system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits
383system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits
384system.cpu.icache.overall_hits::total 78126184 # number of overall hits
385system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
386system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

439system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
440system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
441system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency
442system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency
443system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
444system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
445system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
446system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency

447system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

436system.cpu.l2cache.tags.replacements 95333 # number of replacements
437system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use
438system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
439system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks.
440system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks.
441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
442system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor
443system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id
452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id
454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id
455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id
456system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses
457system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses

448system.cpu.l2cache.tags.replacements 95333 # number of replacements
449system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use
450system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
451system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks.
452system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks.
453system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
454system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor
455system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

462system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
463system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id
464system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id
465system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id
466system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id
467system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id
468system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses
469system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses

470system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

458system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits
459system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits
460system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits
461system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits
462system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits
463system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits
464system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits
465system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits

--- 130 unchanged lines hidden (view full) ---

596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
597system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
598system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
599system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
600system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
601system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter.
602system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
603system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

471system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits
472system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits
473system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits
474system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits
475system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits
476system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits
477system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits
478system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits

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609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
610system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
611system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
612system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
613system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
614system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter.
615system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
616system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

617system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states

604system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution

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628system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram
630system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks)
631system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
632system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
633system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
634system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
635system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

618system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
619system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
620system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution
621system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution
622system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
623system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
624system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution
625system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution

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642system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
643system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram
644system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks)
645system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
646system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
647system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
648system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
649system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

650system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states