| stats.txt (11388:bd4125134e77) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated 4sim_ticks 128076834500 # Number of ticks simulated 5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated 4sim_ticks 128076834500 # Number of ticks simulated 5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 508798 # Simulator instruction rate (inst/s) 8host_op_rate 649592 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 925989388 # Simulator tick rate (ticks/s) 10host_mem_usage 253236 # Number of bytes of host memory used 11host_seconds 138.31 # Real time elapsed on the host | 7host_inst_rate 775777 # Simulator instruction rate (inst/s) 8host_op_rate 990450 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1411878896 # Simulator tick rate (ticks/s) 10host_mem_usage 277764 # Number of bytes of host memory used 11host_seconds 90.71 # Real time elapsed on the host |
| 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory --- 275 unchanged lines hidden (view full) --- 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory --- 275 unchanged lines hidden (view full) --- 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 305system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks 306system.cpu.dcache.writebacks::total 128175 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits 308system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits 309system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits 310system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits 311system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits 312system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 345system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency | 303system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks 304system.cpu.dcache.writebacks::total 128175 # number of writebacks 305system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits 306system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits 307system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits 308system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits 309system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits 310system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency 344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency 345system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 346system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 348system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 350system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency |
| 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 354system.cpu.icache.tags.replacements 16890 # number of replacements 355system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use 356system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 357system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 358system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 360system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor 361system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 405system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency 407system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 412system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 351system.cpu.icache.tags.replacements 16890 # number of replacements 352system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use 353system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 354system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 355system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 356system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 357system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor 358system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 402system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency 404system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 413system.cpu.icache.fast_writes 0 # number of fast writes performed 414system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 415system.cpu.icache.writebacks::writebacks 16890 # number of writebacks 416system.cpu.icache.writebacks::total 16890 # number of writebacks 417system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 418system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 419system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 420system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 421system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 422system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 434system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency | 410system.cpu.icache.writebacks::writebacks 16890 # number of writebacks 411system.cpu.icache.writebacks::total 16890 # number of writebacks 412system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 413system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 414system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 415system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 416system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 417system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 428system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 429system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency |
| 441system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 442system.cpu.l2cache.tags.replacements 95333 # number of replacements 443system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use 444system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. 445system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. 446system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. 447system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 448system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor 449system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency 543system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency 544system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 545system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 546system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 547system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 548system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 549system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 436system.cpu.l2cache.tags.replacements 95333 # number of replacements 437system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use 438system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. 439system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor 443system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 536system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 550system.cpu.l2cache.fast_writes 0 # number of fast writes performed 551system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 552system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks 553system.cpu.l2cache.writebacks::total 86150 # number of writebacks 554system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses 555system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses 556system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses 557system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses 558system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses 559system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 598system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency 599system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency 600system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency 601system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 602system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency 603system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency 604system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 605system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency | 544system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks 545system.cpu.l2cache.writebacks::total 86150 # number of writebacks 546system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses 547system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses 548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses 549system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses 550system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses 551system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 590system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency 591system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency 593system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 594system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency 595system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency 596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 597system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency |
| 606system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 607system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 608system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 609system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 610system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. 611system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 612system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 613system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution --- 57 unchanged lines hidden --- | 598system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. 602system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 603system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution --- 57 unchanged lines hidden --- |