Cross Reference: /gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt

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stats.txt (11336:b318499f676c)	stats.txt (11388:bd4125134e77)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated
4sim_ticks 128076812500 # Number of ticks simulated 5final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)	4sim_ticks 128076834500 # Number of ticks simulated 5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks	6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 887065 # Simulator instruction rate (inst/s) 8host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1614418321 # Simulator tick rate (ticks/s) 10host_mem_usage 277452 # Number of bytes of host memory used 11host_seconds 79.33 # Real time elapsed on the host 12sim_insts 70373629 # Number of instructions simulated 13sim_ops 89847363 # Number of ops (including micro ops) simulated	7host_inst_rate 508798 # Simulator instruction rate (inst/s) 8host_op_rate 649592 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 925989388 # Simulator tick rate (ticks/s) 10host_mem_usage 253236 # Number of bytes of host memory used 11host_seconds 138.31 # Real time elapsed on the host 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory	14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 1820408 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 61878867 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 63699274 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1820408 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1820408 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 43049166 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 43049166 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 43049166 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1820408 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 61878867 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 106748441 # Total bandwidth to/from this memory (bytes/s)	28system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)
39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 1946 # Number of system calls	39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 1946 # Number of system calls
157system.cpu.numCycles 256153625 # number of cpu cycles simulated	157system.cpu.numCycles 256153669 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed	158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 70373629 # Number of instructions committed 161system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses	160system.cpu.committedInsts 70373651 # Number of instructions committed 161system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 164system.cpu.num_func_calls 3311620 # number of times a function call or return occured	163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 164system.cpu.num_func_calls 3311620 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls 166system.cpu.num_int_insts 81528488 # number of integer instructions	165system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls 166system.cpu.num_int_insts 81528528 # number of integer instructions
167system.cpu.num_fp_insts 56 # number of float instructions	167system.cpu.num_fp_insts 56 # number of float instructions
168system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read 169system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written	168system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read 169system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
170system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 20 # number of times the floating registers were written	170system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written	172system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
174system.cpu.num_mem_refs 43422001 # number of memory refs 175system.cpu.num_load_insts 22866262 # Number of load instructions 176system.cpu.num_store_insts 20555739 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles	174system.cpu.num_mem_refs 43422001 # number of memory refs 175system.cpu.num_load_insts 22866262 # Number of load instructions 176system.cpu.num_store_insts 20555739 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
178system.cpu.num_busy_cycles 256153624.998000 # Number of busy cycles	178system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles
179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles	179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 13741486 # Number of branches fetched	181system.cpu.Branches 13741468 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction	182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction	183system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
184system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction --- 16 unchanged lines hidden (view full) --- 208system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction	184system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction --- 16 unchanged lines hidden (view full) --- 208system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 90690084 # Class of executed instruction	216system.cpu.op_class::total 90690106 # Class of executed instruction
217system.cpu.dcache.tags.replacements 155902 # number of replacements	217system.cpu.dcache.tags.replacements 155902 # number of replacements
218system.cpu.dcache.tags.tagsinuse 4075.927151 # Cycle average of tags in use	218system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
219system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.	219system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927151 # Average occupied blocks per requestor	223system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor
224system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id 230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses --- 115 unchanged lines hidden (view full) --- 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354system.cpu.icache.tags.replacements 16890 # number of replacements	224system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id 230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses --- 115 unchanged lines hidden (view full) --- 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354system.cpu.icache.tags.replacements 16890 # number of replacements
355system.cpu.icache.tags.tagsinuse 1732.356647 # Cycle average of tags in use 356system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks.	355system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use 356system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks.
357system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.	357system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
358system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks.	358system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks.
359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.	359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
360system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356647 # Average occupied blocks per requestor	360system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor
361system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id	361system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
369system.cpu.icache.tags.tag_accesses 156309048 # Number of tag accesses 370system.cpu.icache.tags.data_accesses 156309048 # Number of data accesses 371system.cpu.icache.ReadReq_hits::cpu.inst 78126162 # number of ReadReq hits 372system.cpu.icache.ReadReq_hits::total 78126162 # number of ReadReq hits 373system.cpu.icache.demand_hits::cpu.inst 78126162 # number of demand (read+write) hits 374system.cpu.icache.demand_hits::total 78126162 # number of demand (read+write) hits 375system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits 376system.cpu.icache.overall_hits::total 78126162 # number of overall hits	369system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 370system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses 371system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 372system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 373system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 374system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 375system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 376system.cpu.icache.overall_hits::total 78126184 # number of overall hits
377system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 382system.cpu.icache.overall_misses::total 18908 # number of overall misses 383system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles 384system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles 385system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles 386system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles 387system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles 388system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles	377system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 382system.cpu.icache.overall_misses::total 18908 # number of overall misses 383system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles 384system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles 385system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles 386system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles 387system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles 388system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles
389system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) 390system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses 392system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses 393system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses 394system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses	389system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) 390system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses 392system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses 393system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses 394system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses
395system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 396system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 397system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 398system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 399system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 400system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses 401system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency 402system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency --- 32 unchanged lines hidden (view full) --- 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 441system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.l2cache.tags.replacements 95333 # number of replacements	395system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 396system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 397system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 398system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 399system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 400system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses 401system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency 402system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency --- 32 unchanged lines hidden (view full) --- 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 441system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.l2cache.tags.replacements 95333 # number of replacements
443system.cpu.l2cache.tags.tagsinuse 30336.891349 # Cycle average of tags in use	443system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use