| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.127293 # Number of seconds simulated 4sim_ticks 127292683500 # Number of ticks simulated 5final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.127296 # Number of seconds simulated 4sim_ticks 127296402500 # Number of ticks simulated 5final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 884807 # Simulator instruction rate (inst/s) 8host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1600449674 # Simulator tick rate (ticks/s) 10host_mem_usage 320712 # Number of bytes of host memory used 11host_seconds 79.54 # Real time elapsed on the host | 7host_inst_rate 692014 # Simulator instruction rate (inst/s) 8host_op_rate 883507 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1251758978 # Simulator tick rate (ticks/s) 10host_mem_usage 324360 # Number of bytes of host memory used 11host_seconds 101.69 # Real time elapsed on the host |
| 12sim_insts 70373629 # Number of instructions simulated 13sim_ops 89847363 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory | 12sim_insts 70373629 # Number of instructions simulated 13sim_ops 89847363 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory |
| 28system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s) | 28system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s) |
| 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 1946 # Number of system calls | 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 157system.cpu.numCycles 254585367 # number of cpu cycles simulated | 157system.cpu.numCycles 254592805 # number of cpu cycles simulated |
| 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 70373629 # Number of instructions committed 161system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 164system.cpu.num_func_calls 3311620 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 170system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written 174system.cpu.num_mem_refs 43422001 # number of memory refs 175system.cpu.num_load_insts 22866262 # Number of load instructions 176system.cpu.num_store_insts 20555739 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 70373629 # Number of instructions committed 161system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 164system.cpu.num_func_calls 3311620 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 170system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written 174system.cpu.num_mem_refs 43422001 # number of memory refs 175system.cpu.num_load_insts 22866262 # Number of load instructions 176system.cpu.num_store_insts 20555739 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 178system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles | 178system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles |
| 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 13741486 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction 184system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 90690084 # Class of executed instruction 217system.cpu.dcache.tags.replacements 155902 # number of replacements | 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 13741486 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction 184system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 213system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 90690084 # Class of executed instruction 217system.cpu.dcache.tags.replacements 155902 # number of replacements |
| 218system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use | 218system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use |
| 219system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. | 219system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. |
| 222system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor | 222system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor |
| 224system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id | 224system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id |
| 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id | 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id |
| 230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 232system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses 233system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits 234system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits 235system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 236system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 237system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits --- 11 unchanged lines hidden (view full) --- 249system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses 250system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses 251system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses 252system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses 253system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses 254system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses 255system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses 256system.cpu.dcache.overall_misses::total 177392 # number of overall misses | 230system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 232system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses 233system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits 234system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits 235system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 236system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 237system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits --- 11 unchanged lines hidden (view full) --- 249system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses 250system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses 251system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses 252system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses 253system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses 254system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses 255system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses 256system.cpu.dcache.overall_misses::total 177392 # number of overall misses |
| 257system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles 258system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles | 257system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles 258system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles |
| 259system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles 260system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles | 259system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles 260system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles |
| 261system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles 262system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles 263system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles 264system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles | 261system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles 262system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles 263system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles 264system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles |
| 265system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) 266system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) 267system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 268system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 269system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) 270system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) 271system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 272system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 281system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses 282system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses 283system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses 284system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses 285system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses 286system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses 287system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses 288system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses | 265system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) 266system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) 267system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 268system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 269system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) 270system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) 271system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 272system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 281system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses 282system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses 283system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses 284system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses 285system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses 286system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses 287system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses 288system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses |
| 289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency 290system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency | 289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency 290system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency |
| 291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency 292system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency | 291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency 292system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency |
| 293system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency 294system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency | 293system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency 294system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency |
| 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 315system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses 316system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses 317system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses 318system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses 319system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses 320system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses 321system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses 322system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses | 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 315system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses 316system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses 317system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses 318system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses 319system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses 320system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses 321system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses 322system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses |
| 323system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles 324system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles | 323system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles 324system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles |
| 325system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles 326system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles 327system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles 328system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles | 325system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles 326system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles 327system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles 328system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles |
| 329system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles 330system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles 331system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles 332system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles | 329system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles 330system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles 331system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles 332system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles |
| 333system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses 334system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses 335system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 336system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 337system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses 338system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses 339system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses 340system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses 341system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 342system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses | 333system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses 334system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses 335system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 336system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 337system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses 338system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses 339system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses 340system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses 341system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 342system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| 343system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency 344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency | 343system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency 344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency |
| 345system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency | 345system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency |
| 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency | 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency |
| 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354system.cpu.icache.tags.replacements 16890 # number of replacements | 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354system.cpu.icache.tags.replacements 16890 # number of replacements |
| 355system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use | 355system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use |
| 356system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. 357system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 358system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. 359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 356system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. 357system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 358system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. 359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 360system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor | 360system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor |
| 361system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 375system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits 376system.cpu.icache.overall_hits::total 78126162 # number of overall hits 377system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 382system.cpu.icache.overall_misses::total 18908 # number of overall misses | 361system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 375system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits 376system.cpu.icache.overall_hits::total 78126162 # number of overall hits 377system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 382system.cpu.icache.overall_misses::total 18908 # number of overall misses |
| 383system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles 384system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles 385system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles 386system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles 387system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles 388system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles | 383system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles 384system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles 385system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles 386system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles 387system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles 388system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles |
| 389system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) 390system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses 392system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses 393system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses 394system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses 395system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 396system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 397system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 398system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 399system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 400system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses | 389system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) 390system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses 392system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses 393system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses 394system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses 395system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 396system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 397system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 398system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 399system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 400system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses |
| 401system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency 402system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency 403system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency 404system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency 405system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency | 401system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency 402system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency 403system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency 404system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency 405system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency |
| 407system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 412system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 413system.cpu.icache.fast_writes 0 # number of fast writes performed 414system.cpu.icache.cache_copies 0 # number of cache copies performed 415system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 416system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 417system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 418system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 419system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 420system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses | 407system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 412system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 413system.cpu.icache.fast_writes 0 # number of fast writes performed 414system.cpu.icache.cache_copies 0 # number of cache copies performed 415system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 416system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 417system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 418system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 419system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 420system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses |
| 421system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles 423system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles 424system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles 425system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles 426system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles | 421system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles 423system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles 424system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles 425system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles 426system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles |
| 427system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses 428system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses 429system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses 430system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses 431system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 432system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses | 427system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses 428system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses 429system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses 430system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses 431system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 432system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses |
| 433system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency 435system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency 437system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency | 433system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency 435system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency 437system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency |
| 439system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 440system.cpu.l2cache.tags.replacements 94651 # number of replacements | 439system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 440system.cpu.l2cache.tags.replacements 94651 # number of replacements |
| 441system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use | 441system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use |
| 442system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. 443system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. 444system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. 445system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 442system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. 443system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. 444system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. 445system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 446system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor 447system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor 448system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor | 446system.cpu.l2cache.tags.occ_blocks::writebacks 27670.382318 # Average occupied blocks per requestor 447system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.500039 # Average occupied blocks per requestor 448system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.601472 # Average occupied blocks per requestor |
| 449system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy 450system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy 451system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy 452system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy 453system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id | 449system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy 450system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy 451system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy 452system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy 453system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id |
| 455system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id | 455system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id |
| 457system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 459system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id 460system.cpu.l2cache.tags.tag_accesses 3016794 # Number of tag accesses 461system.cpu.l2cache.tags.data_accesses 3016794 # Number of data accesses 462system.cpu.l2cache.Writeback_hits::writebacks 128193 # number of Writeback hits 463system.cpu.l2cache.Writeback_hits::total 128193 # number of Writeback hits 464system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits --- 17 unchanged lines hidden (view full) --- 482system.cpu.l2cache.demand_misses::cpu.inst 3950 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses 484system.cpu.l2cache.demand_misses::total 127770 # number of demand (read+write) misses 485system.cpu.l2cache.overall_misses::cpu.inst 3950 # number of overall misses 486system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses 487system.cpu.l2cache.overall_misses::total 127770 # number of overall misses 488system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371653500 # number of ReadExReq miss cycles 489system.cpu.l2cache.ReadExReq_miss_latency::total 5371653500 # number of ReadExReq miss cycles | 457system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 459system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id 460system.cpu.l2cache.tags.tag_accesses 3016794 # Number of tag accesses 461system.cpu.l2cache.tags.data_accesses 3016794 # Number of data accesses 462system.cpu.l2cache.Writeback_hits::writebacks 128193 # number of Writeback hits 463system.cpu.l2cache.Writeback_hits::total 128193 # number of Writeback hits 464system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits --- 17 unchanged lines hidden (view full) --- 482system.cpu.l2cache.demand_misses::cpu.inst 3950 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses 484system.cpu.l2cache.demand_misses::total 127770 # number of demand (read+write) misses 485system.cpu.l2cache.overall_misses::cpu.inst 3950 # number of overall misses 486system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses 487system.cpu.l2cache.overall_misses::total 127770 # number of overall misses 488system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371653500 # number of ReadExReq miss cycles 489system.cpu.l2cache.ReadExReq_miss_latency::total 5371653500 # number of ReadExReq miss cycles |
| 490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207971500 # number of ReadCleanReq miss cycles 491system.cpu.l2cache.ReadCleanReq_miss_latency::total 207971500 # number of ReadCleanReq miss cycles 492system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133068500 # number of ReadSharedReq miss cycles 493system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133068500 # number of ReadSharedReq miss cycles 494system.cpu.l2cache.demand_miss_latency::cpu.inst 207971500 # number of demand (read+write) miss cycles 495system.cpu.l2cache.demand_miss_latency::cpu.data 6504722000 # number of demand (read+write) miss cycles 496system.cpu.l2cache.demand_miss_latency::total 6712693500 # number of demand (read+write) miss cycles 497system.cpu.l2cache.overall_miss_latency::cpu.inst 207971500 # number of overall miss cycles 498system.cpu.l2cache.overall_miss_latency::cpu.data 6504722000 # number of overall miss cycles 499system.cpu.l2cache.overall_miss_latency::total 6712693500 # number of overall miss cycles | 490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207973500 # number of ReadCleanReq miss cycles 491system.cpu.l2cache.ReadCleanReq_miss_latency::total 207973500 # number of ReadCleanReq miss cycles 492system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133133500 # number of ReadSharedReq miss cycles 493system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133133500 # number of ReadSharedReq miss cycles 494system.cpu.l2cache.demand_miss_latency::cpu.inst 207973500 # number of demand (read+write) miss cycles 495system.cpu.l2cache.demand_miss_latency::cpu.data 6504787000 # number of demand (read+write) miss cycles 496system.cpu.l2cache.demand_miss_latency::total 6712760500 # number of demand (read+write) miss cycles 497system.cpu.l2cache.overall_miss_latency::cpu.inst 207973500 # number of overall miss cycles 498system.cpu.l2cache.overall_miss_latency::cpu.data 6504787000 # number of overall miss cycles 499system.cpu.l2cache.overall_miss_latency::total 6712760500 # number of overall miss cycles |
| 500system.cpu.l2cache.Writeback_accesses::writebacks 128193 # number of Writeback accesses(hits+misses) 501system.cpu.l2cache.Writeback_accesses::total 128193 # number of Writeback accesses(hits+misses) 502system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) 505system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) 506system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) 507system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 520system.cpu.l2cache.demand_miss_rate::cpu.inst 0.208906 # miss rate for demand accesses 521system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses 522system.cpu.l2cache.demand_miss_rate::total 0.714174 # miss rate for demand accesses 523system.cpu.l2cache.overall_miss_rate::cpu.inst 0.208906 # miss rate for overall accesses 524system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses 525system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses 526system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency 527system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency | 500system.cpu.l2cache.Writeback_accesses::writebacks 128193 # number of Writeback accesses(hits+misses) 501system.cpu.l2cache.Writeback_accesses::total 128193 # number of Writeback accesses(hits+misses) 502system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) 505system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) 506system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) 507system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 520system.cpu.l2cache.demand_miss_rate::cpu.inst 0.208906 # miss rate for demand accesses 521system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses 522system.cpu.l2cache.demand_miss_rate::total 0.714174 # miss rate for demand accesses 523system.cpu.l2cache.overall_miss_rate::cpu.inst 0.208906 # miss rate for overall accesses 524system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses 525system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses 526system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency 527system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency |
| 528system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658 # average ReadCleanReq miss latency 529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658 # average ReadCleanReq miss latency 530system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429 # average ReadSharedReq miss latency 531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429 # average ReadSharedReq miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency 533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency 534system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967 # average overall miss latency 535system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967 # average overall miss latency | 528system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency 529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency 530system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency 531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency 533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency 534system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency 535system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency |
| 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 556system.cpu.l2cache.demand_mshr_misses::cpu.inst 3950 # number of demand (read+write) MSHR misses 557system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses 558system.cpu.l2cache.demand_mshr_misses::total 127770 # number of demand (read+write) MSHR misses 559system.cpu.l2cache.overall_mshr_misses::cpu.inst 3950 # number of overall MSHR misses 560system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses 561system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles 563system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles | 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 556system.cpu.l2cache.demand_mshr_misses::cpu.inst 3950 # number of demand (read+write) MSHR misses 557system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses 558system.cpu.l2cache.demand_mshr_misses::total 127770 # number of demand (read+write) MSHR misses 559system.cpu.l2cache.overall_mshr_misses::cpu.inst 3950 # number of overall MSHR misses 560system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses 561system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles 563system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles |
| 564system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles 565system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles 566system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles 567system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles 568system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles 569system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles 570system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles 571system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles 572system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles 573system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles | 564system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles 565system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles 566system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles 567system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles 568system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles 569system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles 570system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles 571system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles 572system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles 573system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles |
| 574system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 575system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 576system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for ReadCleanReq accesses 579system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.208906 # mshr miss rate for ReadCleanReq accesses 580system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadSharedReq accesses 581system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406676 # mshr miss rate for ReadSharedReq accesses 582system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for demand accesses 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses 584system.cpu.l2cache.demand_mshr_miss_rate::total 0.714174 # mshr miss rate for demand accesses 585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for overall accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses 587system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses 588system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency 589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency | 574system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 575system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 576system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for ReadCleanReq accesses 579system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.208906 # mshr miss rate for ReadCleanReq accesses 580system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadSharedReq accesses 581system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406676 # mshr miss rate for ReadSharedReq accesses 582system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for demand accesses 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses 584system.cpu.l2cache.demand_mshr_miss_rate::total 0.714174 # mshr miss rate for demand accesses 585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for overall accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses 587system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses 588system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency 589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency |
| 590system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency 591system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency 592system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency 593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency 594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency 595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency 596system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency 597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency 598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency 599system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency | 590system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency 591system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency 592system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency 593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency 594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency 595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency 596system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency 597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency 598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency 599system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency |
| 600system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 600system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 601system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 602system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 603system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter. 605system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 606system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 601system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution 608system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.snoops 94651 # Total snoops (count) 615system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram | 607system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution 614system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes) 619system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) 620system.cpu.toL2Bus.snoops 94651 # Total snoops (count) 621system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram |
| 616system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram | 622system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram |
| 618system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 624system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 619system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram | 625system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram |
| 622system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 628system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 623system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 629system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 624system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram 626system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) 627system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 628system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 629system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 630system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 631system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) --- 27 unchanged lines hidden --- | 630system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram 632system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) 633system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 634system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 635system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 636system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 637system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) --- 27 unchanged lines hidden --- |