3,5c3,5
< sim_seconds 0.127293 # Number of seconds simulated
< sim_ticks 127292683500 # Number of ticks simulated
< final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.127296 # Number of seconds simulated
> sim_ticks 127296402500 # Number of ticks simulated
> final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 884807 # Simulator instruction rate (inst/s)
< host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1600449674 # Simulator tick rate (ticks/s)
< host_mem_usage 320712 # Number of bytes of host memory used
< host_seconds 79.54 # Real time elapsed on the host
---
> host_inst_rate 692014 # Simulator instruction rate (inst/s)
> host_op_rate 883507 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1251758978 # Simulator tick rate (ticks/s)
> host_mem_usage 324360 # Number of bytes of host memory used
> host_seconds 101.69 # Real time elapsed on the host
28,38c28,38
< system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 254585367 # number of cpu cycles simulated
---
> system.cpu.numCycles 254592805 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor
228,229c228,229
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id
257,258c257,258
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles
261,264c261,264
< system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles
289,290c289,290
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency
293,296c293,296
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency
323,324c323,324
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles
329,332c329,332
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles
343,344c343,344
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency
349,352c349,352
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency
355c355
< system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use
360c360
< system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor
383,388c383,388
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles
401,406c401,406
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency
421,426c421,426
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles
433,438c433,438
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency
441c441
< system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use
446,448c446,448
< system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 27670.382318 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.500039 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.601472 # Average occupied blocks per requestor
455,456c455,456
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id
490,499c490,499
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207971500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 207971500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133068500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133068500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 207971500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6504722000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 6712693500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 207971500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6504722000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 6712693500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207973500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 207973500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133133500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133133500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 207973500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6504787000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 6712760500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 207973500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6504787000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 6712760500 # number of overall miss cycles
528,537c528,537
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency
564,573c564,573
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles
590,599c590,599
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency
600a601,606
> system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
616,617c622,623
< system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram
619,621c625,627
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
623c629
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_seconds 0.127293 # Number of seconds simulated
< sim_ticks 127292683500 # Number of ticks simulated
< final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.127296 # Number of seconds simulated
> sim_ticks 127296402500 # Number of ticks simulated
> final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 884807 # Simulator instruction rate (inst/s)
< host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1600449674 # Simulator tick rate (ticks/s)
< host_mem_usage 320712 # Number of bytes of host memory used
< host_seconds 79.54 # Real time elapsed on the host
---
> host_inst_rate 692014 # Simulator instruction rate (inst/s)
> host_op_rate 883507 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1251758978 # Simulator tick rate (ticks/s)
> host_mem_usage 324360 # Number of bytes of host memory used
> host_seconds 101.69 # Real time elapsed on the host
28,38c28,38
< system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 254585367 # number of cpu cycles simulated
---
> system.cpu.numCycles 254592805 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor
228,229c228,229
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id
257,258c257,258
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles
261,264c261,264
< system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles
289,290c289,290
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency
293,296c293,296
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency
323,324c323,324
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles
329,332c329,332
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles
343,344c343,344
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency
349,352c349,352
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency
355c355
< system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use
360c360
< system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor
383,388c383,388
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles
401,406c401,406
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency
421,426c421,426
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles
433,438c433,438
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency
441c441
< system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use
446,448c446,448
< system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 27670.382318 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.500039 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.601472 # Average occupied blocks per requestor
455,456c455,456
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id
490,499c490,499
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207971500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 207971500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133068500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133068500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 207971500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6504722000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 6712693500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 207971500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6504722000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 6712693500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207973500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 207973500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133133500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133133500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 207973500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6504787000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 6712760500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 207973500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6504787000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 6712760500 # number of overall miss cycles
528,537c528,537
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency
564,573c564,573
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles
590,599c590,599
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency
600a601,606
> system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
616,617c622,623
< system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram
619,621c625,627
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
623c629
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram