Cross Reference: /gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt

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stats.txt (11731:c473ca7cc650)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128204 # Number of seconds simulated 4sim_ticks 128204299500 # Number of ticks simulated 5final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 442445 # Simulator instruction rate (inst/s) 8host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 806030069 # Simulator tick rate (ticks/s) 10host_mem_usage 262052 # Number of bytes of host memory used 11host_seconds 159.06 # Real time elapsed on the host 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 53system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 54system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 56system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dtb.inst_hits 0 # ITB inst hits 82system.cpu.dtb.inst_misses 0 # ITB inst misses 83system.cpu.dtb.read_hits 0 # DTB read hits 84system.cpu.dtb.read_misses 0 # DTB read misses 85system.cpu.dtb.write_hits 0 # DTB write hits 86system.cpu.dtb.write_misses 0 # DTB write misses 87system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 91system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 92system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 93system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141system.cpu.itb.inst_hits 0 # ITB inst hits 142system.cpu.itb.inst_misses 0 # ITB inst misses 143system.cpu.itb.read_hits 0 # DTB read hits 144system.cpu.itb.read_misses 0 # DTB read misses 145system.cpu.itb.write_hits 0 # DTB write hits 146system.cpu.itb.write_misses 0 # DTB write misses 147system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 150system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128204 # Number of seconds simulated 4sim_ticks 128204299500 # Number of ticks simulated 5final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 442445 # Simulator instruction rate (inst/s) 8host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 806030069 # Simulator tick rate (ticks/s) 10host_mem_usage 262052 # Number of bytes of host memory used 11host_seconds 159.06 # Real time elapsed on the host 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 53system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 54system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 56system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dtb.inst_hits 0 # ITB inst hits 82system.cpu.dtb.inst_misses 0 # ITB inst misses 83system.cpu.dtb.read_hits 0 # DTB read hits 84system.cpu.dtb.read_misses 0 # DTB read misses 85system.cpu.dtb.write_hits 0 # DTB write hits 86system.cpu.dtb.write_misses 0 # DTB write misses 87system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 91system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 92system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 93system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141system.cpu.itb.inst_hits 0 # ITB inst hits 142system.cpu.itb.inst_misses 0 # ITB inst misses 143system.cpu.itb.read_hits 0 # DTB read hits 144system.cpu.itb.read_misses 0 # DTB read misses 145system.cpu.itb.write_hits 0 # DTB write hits 146system.cpu.itb.write_misses 0 # DTB write misses 147system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 150system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses
162system.cpu.workload.num_syscalls 1946 # Number of system calls	162system.cpu.workload.numSyscalls 1946 # Number of system calls
163system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 256408599 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 70373651 # Number of instructions committed 168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 171system.cpu.num_func_calls 3311620 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls 173system.cpu.num_int_insts 81528528 # number of integer instructions 174system.cpu.num_fp_insts 56 # number of float instructions 175system.cpu.num_int_register_reads 141328435 # number of times the integer registers were read 176system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written 177system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written 181system.cpu.num_mem_refs 43422001 # number of memory refs 182system.cpu.num_load_insts 22866262 # Number of load instructions 183system.cpu.num_store_insts 20555739 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 185system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 13741468 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction 191system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction 194system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction 195system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction 196system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction 197system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction 198system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction 199system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction 200system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction 201system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction 202system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction 203system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction 204system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction 205system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction 206system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction 207system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction 208system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction 209system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction 213system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction 214system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction 215system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction 216system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction 217system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction 218system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 219system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 220system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 221system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction 222system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction 223system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction 224system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction 225system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 227system.cpu.op_class::total 90690106 # Class of executed instruction 228system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 229system.cpu.dcache.tags.replacements 155902 # number of replacements 230system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use 231system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. 232system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 233system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. 234system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. 235system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor 236system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy 237system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy 238system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 240system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id 241system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id 242system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 243system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 244system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses 245system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 246system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits 247system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits 248system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 249system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 250system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits 251system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits 252system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 253system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 254system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 255system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 256system.cpu.dcache.demand_hits::cpu.data 42486195 # number of demand (read+write) hits 257system.cpu.dcache.demand_hits::total 42486195 # number of demand (read+write) hits 258system.cpu.dcache.overall_hits::cpu.data 42569752 # number of overall hits 259system.cpu.dcache.overall_hits::total 42569752 # number of overall hits 260system.cpu.dcache.ReadReq_misses::cpu.data 36741 # number of ReadReq misses 261system.cpu.dcache.ReadReq_misses::total 36741 # number of ReadReq misses 262system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses 263system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses 264system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 # number of SoftPFReq misses 265system.cpu.dcache.SoftPFReq_misses::total 40187 # number of SoftPFReq misses 266system.cpu.dcache.demand_misses::cpu.data 143773 # number of demand (read+write) misses 267system.cpu.dcache.demand_misses::total 143773 # number of demand (read+write) misses 268system.cpu.dcache.overall_misses::cpu.data 183960 # number of overall misses 269system.cpu.dcache.overall_misses::total 183960 # number of overall misses 270system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 # number of ReadReq miss cycles 271system.cpu.dcache.ReadReq_miss_latency::total 594992500 # number of ReadReq miss cycles 272system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 # number of WriteReq miss cycles 273system.cpu.dcache.WriteReq_miss_latency::total 6509368500 # number of WriteReq miss cycles 274system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 # number of demand (read+write) miss cycles 275system.cpu.dcache.demand_miss_latency::total 7104361000 # number of demand (read+write) miss cycles 276system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 # number of overall miss cycles 277system.cpu.dcache.overall_miss_latency::total 7104361000 # number of overall miss cycles 278system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) 279system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) 280system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 281system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 282system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) 283system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) 284system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 285system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 286system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 287system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 288system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses 289system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses 290system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses 291system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses 292system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 # miss rate for ReadReq accesses 293system.cpu.dcache.ReadReq_miss_rate::total 0.001613 # miss rate for ReadReq accesses 294system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses 295system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses 296system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 # miss rate for SoftPFReq accesses 297system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 # miss rate for SoftPFReq accesses 298system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 # miss rate for demand accesses 299system.cpu.dcache.demand_miss_rate::total 0.003373 # miss rate for demand accesses 300system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 # miss rate for overall accesses 301system.cpu.dcache.overall_miss_rate::total 0.004303 # miss rate for overall accesses 302system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 # average ReadReq miss latency 303system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 # average ReadReq miss latency 304system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 # average WriteReq miss latency 305system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 # average WriteReq miss latency 306system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 # average overall miss latency 307system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 # average overall miss latency 308system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 # average overall miss latency 309system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 # average overall miss latency 310system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 313system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 314system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.cpu.dcache.writebacks::writebacks 127926 # number of writebacks 317system.cpu.dcache.writebacks::total 127926 # number of writebacks 318system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 # number of ReadReq MSHR hits 319system.cpu.dcache.ReadReq_mshr_hits::total 7633 # number of ReadReq MSHR hits 320system.cpu.dcache.demand_mshr_hits::cpu.data 7633 # number of demand (read+write) MSHR hits 321system.cpu.dcache.demand_mshr_hits::total 7633 # number of demand (read+write) MSHR hits 322system.cpu.dcache.overall_mshr_hits::cpu.data 7633 # number of overall MSHR hits 323system.cpu.dcache.overall_mshr_hits::total 7633 # number of overall MSHR hits 324system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses 325system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses 326system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses 327system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses 328system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses 329system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses 330system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses 331system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses 332system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses 333system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses 334system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 # number of ReadReq MSHR miss cycles 335system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 # number of ReadReq MSHR miss cycles 336system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 # number of WriteReq MSHR miss cycles 337system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 # number of WriteReq MSHR miss cycles 338system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 # number of SoftPFReq MSHR miss cycles 339system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 # number of SoftPFReq MSHR miss cycles 340system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 # number of demand (read+write) MSHR miss cycles 341system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 # number of demand (read+write) MSHR miss cycles 342system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 # number of overall MSHR miss cycles 343system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 # number of overall MSHR miss cycles 344system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses 345system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses 346system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 347system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 348system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses 349system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses 350system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses 351system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses 352system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 353system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses 354system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 # average ReadReq mshr miss latency 355system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 # average ReadReq mshr miss latency 356system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency 357system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency 358system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency 359system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency 360system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency 361system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency 362system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency 363system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency 364system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 365system.cpu.icache.tags.replacements 16890 # number of replacements 366system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use 367system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 368system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 369system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 370system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 371system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor 372system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy 373system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy 374system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 375system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 376system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 379system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 380system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses 382system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 383system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 384system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 385system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 386system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 387system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 388system.cpu.icache.overall_hits::total 78126184 # number of overall hits 389system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 390system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 391system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 392system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 393system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 394system.cpu.icache.overall_misses::total 18908 # number of overall misses 395system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 # number of ReadReq miss cycles 396system.cpu.icache.ReadReq_miss_latency::total 429951000 # number of ReadReq miss cycles 397system.cpu.icache.demand_miss_latency::cpu.inst 429951000 # number of demand (read+write) miss cycles 398system.cpu.icache.demand_miss_latency::total 429951000 # number of demand (read+write) miss cycles 399system.cpu.icache.overall_miss_latency::cpu.inst 429951000 # number of overall miss cycles 400system.cpu.icache.overall_miss_latency::total 429951000 # number of overall miss cycles 401system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) 402system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) 403system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses 404system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses 405system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses 406system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses 407system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 408system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 409system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 410system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 411system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 412system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses 413system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 # average ReadReq miss latency 414system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 # average ReadReq miss latency 415system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency 416system.cpu.icache.demand_avg_miss_latency::total 22739.105141 # average overall miss latency 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency 418system.cpu.icache.overall_avg_miss_latency::total 22739.105141 # average overall miss latency 419system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 420system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 424system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.cpu.icache.writebacks::writebacks 16890 # number of writebacks 426system.cpu.icache.writebacks::total 16890 # number of writebacks 427system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 428system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 429system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 430system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 431system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 432system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses 433system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 # number of ReadReq MSHR miss cycles 434system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 # number of ReadReq MSHR miss cycles 435system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 # number of demand (read+write) MSHR miss cycles 436system.cpu.icache.demand_mshr_miss_latency::total 411043000 # number of demand (read+write) MSHR miss cycles 437system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 # number of overall MSHR miss cycles 438system.cpu.icache.overall_mshr_miss_latency::total 411043000 # number of overall MSHR miss cycles 439system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses 440system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses 441system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses 442system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses 443system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 444system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 445system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency 446system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency 447system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency 449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 450system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency 451system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 452system.cpu.l2cache.tags.replacements 96062 # number of replacements 453system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use 454system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. 455system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. 456system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. 457system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. 458system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor 459system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor 461system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 475system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits 476system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits 477system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 478system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 479system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits 480system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits 481system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits 482system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits 483system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 # number of ReadSharedReq hits 484system.cpu.l2cache.ReadSharedReq_hits::total 31236 # number of ReadSharedReq hits 485system.cpu.l2cache.demand_hits::cpu.inst 15262 # number of demand (read+write) hits 486system.cpu.l2cache.demand_hits::cpu.data 35948 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::total 51210 # number of demand (read+write) hits 488system.cpu.l2cache.overall_hits::cpu.inst 15262 # number of overall hits 489system.cpu.l2cache.overall_hits::cpu.data 35948 # number of overall hits 490system.cpu.l2cache.overall_hits::total 51210 # number of overall hits 491system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 # number of ReadExReq misses 492system.cpu.l2cache.ReadExReq_misses::total 102320 # number of ReadExReq misses 493system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 # number of ReadCleanReq misses 494system.cpu.l2cache.ReadCleanReq_misses::total 3646 # number of ReadCleanReq misses 495system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 # number of ReadSharedReq misses 496system.cpu.l2cache.ReadSharedReq_misses::total 21730 # number of ReadSharedReq misses 497system.cpu.l2cache.demand_misses::cpu.inst 3646 # number of demand (read+write) misses 498system.cpu.l2cache.demand_misses::cpu.data 124050 # number of demand (read+write) misses 499system.cpu.l2cache.demand_misses::total 127696 # number of demand (read+write) misses 500system.cpu.l2cache.overall_misses::cpu.inst 3646 # number of overall misses 501system.cpu.l2cache.overall_misses::cpu.data 124050 # number of overall misses 502system.cpu.l2cache.overall_misses::total 127696 # number of overall misses 503system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 # number of ReadExReq miss cycles 504system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 # number of ReadExReq miss cycles 505system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 # number of ReadCleanReq miss cycles 506system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 # number of ReadCleanReq miss cycles 507system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 # number of ReadSharedReq miss cycles 508system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 # number of ReadSharedReq miss cycles 509system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 # number of demand (read+write) miss cycles 510system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 # number of demand (read+write) miss cycles 511system.cpu.l2cache.demand_miss_latency::total 7728636500 # number of demand (read+write) miss cycles 512system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 # number of overall miss cycles 513system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 # number of overall miss cycles 514system.cpu.l2cache.overall_miss_latency::total 7728636500 # number of overall miss cycles 515system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 # number of WritebackDirty accesses(hits+misses) 516system.cpu.l2cache.WritebackDirty_accesses::total 127926 # number of WritebackDirty accesses(hits+misses) 517system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) 518system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) 519system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) 520system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) 521system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) 522system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) 523system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) 524system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) 525system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses 526system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses 528system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses 531system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 # miss rate for ReadExReq accesses 532system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 # miss rate for ReadExReq accesses 533system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 # miss rate for ReadCleanReq accesses 534system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 # miss rate for ReadCleanReq accesses 535system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 # miss rate for ReadSharedReq accesses 536system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 # miss rate for ReadSharedReq accesses 537system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 # miss rate for demand accesses 538system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 # miss rate for demand accesses 539system.cpu.l2cache.demand_miss_rate::total 0.713760 # miss rate for demand accesses 540system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 # miss rate for overall accesses 541system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 # miss rate for overall accesses 542system.cpu.l2cache.overall_miss_rate::total 0.713760 # miss rate for overall accesses 543system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 # average ReadExReq miss latency 544system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 # average ReadExReq miss latency 545system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 # average ReadCleanReq miss latency 546system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 # average ReadCleanReq miss latency 547system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 # average ReadSharedReq miss latency 548system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 # average ReadSharedReq miss latency 549system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency 550system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency 551system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 # average overall miss latency 552system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 # average overall miss latency 555system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 556system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.l2cache.writebacks::writebacks 86477 # number of writebacks 562system.cpu.l2cache.writebacks::total 86477 # number of writebacks 563system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses 564system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 # number of ReadExReq MSHR misses 566system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 # number of ReadExReq MSHR misses 567system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 # number of ReadCleanReq MSHR misses 568system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 # number of ReadCleanReq MSHR misses 569system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 # number of ReadSharedReq MSHR misses 570system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 # number of ReadSharedReq MSHR misses 571system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 # number of demand (read+write) MSHR misses 572system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 # number of demand (read+write) MSHR misses 573system.cpu.l2cache.demand_mshr_misses::total 127696 # number of demand (read+write) MSHR misses 574system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 # number of overall MSHR misses 575system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 # number of overall MSHR misses 576system.cpu.l2cache.overall_mshr_misses::total 127696 # number of overall MSHR misses 577system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 # number of ReadExReq MSHR miss cycles 578system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 # number of ReadExReq MSHR miss cycles 579system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 # number of ReadCleanReq MSHR miss cycles 580system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 # number of ReadCleanReq MSHR miss cycles 581system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 # number of ReadSharedReq MSHR miss cycles 582system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 # number of ReadSharedReq MSHR miss cycles 583system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 # number of demand (read+write) MSHR miss cycles 584system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 # number of demand (read+write) MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 # number of overall MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 # number of overall MSHR miss cycles 588system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 # number of overall MSHR miss cycles 589system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 590system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 591system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 # mshr miss rate for ReadExReq accesses 592system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 # mshr miss rate for ReadExReq accesses 593system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for ReadCleanReq accesses 594system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 # mshr miss rate for ReadCleanReq accesses 595system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 # mshr miss rate for ReadSharedReq accesses 596system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 # mshr miss rate for ReadSharedReq accesses 597system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for demand accesses 598system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for demand accesses 599system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 # mshr miss rate for demand accesses 600system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for overall accesses 601system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for overall accesses 602system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 # mshr miss rate for overall accesses 603system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 # average ReadExReq mshr miss latency 604system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 # average ReadExReq mshr miss latency 605system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 # average ReadCleanReq mshr miss latency 606system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 # average ReadCleanReq mshr miss latency 607system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 # average ReadSharedReq mshr miss latency 608system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 # average ReadSharedReq mshr miss latency 609system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency 610system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency 611system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency 612system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency 613system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency 614system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency 615system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 616system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 617system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 618system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. 619system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 620system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 621system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 622system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 628system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 629system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution 630system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) 631system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) 632system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) 633system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) 634system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 # Cumulative packet size per connected master and slave (bytes) 635system.cpu.toL2Bus.pkt_size::total 20718208 # Cumulative packet size per connected master and slave (bytes) 636system.cpu.toL2Bus.snoops 96062 # Total snoops (count) 637system.cpu.toL2Bus.snoopTraffic 5534528 # Total snoop traffic (bytes) 638system.cpu.toL2Bus.snoop_fanout::samples 274968 # Request fanout histogram 639system.cpu.toL2Bus.snoop_fanout::mean 0.025367 # Request fanout histogram 640system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 # Request fanout histogram 641system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 642system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% # Request fanout histogram 643system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% # Request fanout histogram 644system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram 645system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 646system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 647system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 648system.cpu.toL2Bus.snoop_fanout::total 274968 # Request fanout histogram 649system.cpu.toL2Bus.reqLayer0.occupancy 320665000 # Layer occupancy (ticks) 650system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 651system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 652system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 653system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 654system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 655system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. 656system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. 657system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 658system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 659system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 660system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 661system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 662system.membus.trans_dist::ReadResp 25376 # Transaction distribution 663system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution 664system.membus.trans_dist::CleanEvict 6466 # Transaction distribution 665system.membus.trans_dist::ReadExReq 102320 # Transaction distribution 666system.membus.trans_dist::ReadExResp 102320 # Transaction distribution 667system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution 668system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) 670system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 # Cumulative packet size per connected master and slave (bytes) 671system.membus.pkt_size::total 13707072 # Cumulative packet size per connected master and slave (bytes) 672system.membus.snoops 0 # Total snoops (count) 673system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 674system.membus.snoop_fanout::samples 127704 # Request fanout histogram 675system.membus.snoop_fanout::mean 0 # Request fanout histogram 676system.membus.snoop_fanout::stdev 0 # Request fanout histogram 677system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 678system.membus.snoop_fanout::0 127704 100.00% 100.00% # Request fanout histogram 679system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 680system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 681system.membus.snoop_fanout::min_value 0 # Request fanout histogram 682system.membus.snoop_fanout::max_value 0 # Request fanout histogram 683system.membus.snoop_fanout::total 127704 # Request fanout histogram 684system.membus.reqLayer0.occupancy 569386372 # Layer occupancy (ticks) 685system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 686system.membus.respLayer1.occupancy 638480000 # Layer occupancy (ticks) 687system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 688 689---------- End Simulation Statistics ----------	163system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 256408599 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 70373651 # Number of instructions committed 168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 171system.cpu.num_func_calls 3311620 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls 173system.cpu.num_int_insts 81528528 # number of integer instructions 174system.cpu.num_fp_insts 56 # number of float instructions 175system.cpu.num_int_register_reads 141328435 # number of times the integer registers were read 176system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written 177system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written 181system.cpu.num_mem_refs 43422001 # number of memory refs 182system.cpu.num_load_insts 22866262 # Number of load instructions 183system.cpu.num_store_insts 20555739 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 185system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 13741468 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction 191system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction 194system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction 195system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction 196system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction 197system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction 198system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction 199system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction 200system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction 201system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction 202system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction 203system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction 204system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction 205system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction 206system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction 207system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction 208system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction 209system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction 213system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction 214system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction 215system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction 216system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction 217system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction 218system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 219system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 220system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 221system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction 222system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction 223system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction 224system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction 225system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 227system.cpu.op_class::total 90690106 # Class of executed instruction 228system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 229system.cpu.dcache.tags.replacements 155902 # number of replacements 230system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use 231system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. 232system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 233system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. 234system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. 235system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor 236system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy 237system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy 238system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 240system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id 241system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id 242system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 243system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 244system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses 245system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 246system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits 247system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits 248system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 249system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 250system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits 251system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits 252system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 253system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 254system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 255system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 256system.cpu.dcache.demand_hits::cpu.data 42486195 # number of demand (read+write) hits 257system.cpu.dcache.demand_hits::total 42486195 # number of demand (read+write) hits 258system.cpu.dcache.overall_hits::cpu.data 42569752 # number of overall hits 259system.cpu.dcache.overall_hits::total 42569752 # number of overall hits 260system.cpu.dcache.ReadReq_misses::cpu.data 36741 # number of ReadReq misses 261system.cpu.dcache.ReadReq_misses::total 36741 # number of ReadReq misses 262system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses 263system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses 264system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 # number of SoftPFReq misses 265system.cpu.dcache.SoftPFReq_misses::total 40187 # number of SoftPFReq misses 266system.cpu.dcache.demand_misses::cpu.data 143773 # number of demand (read+write) misses 267system.cpu.dcache.demand_misses::total 143773 # number of demand (read+write) misses 268system.cpu.dcache.overall_misses::cpu.data 183960 # number of overall misses 269system.cpu.dcache.overall_misses::total 183960 # number of overall misses 270system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 # number of ReadReq miss cycles 271system.cpu.dcache.ReadReq_miss_latency::total 594992500 # number of ReadReq miss cycles 272system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 # number of WriteReq miss cycles 273system.cpu.dcache.WriteReq_miss_latency::total 6509368500 # number of WriteReq miss cycles 274system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 # number of demand (read+write) miss cycles 275system.cpu.dcache.demand_miss_latency::total 7104361000 # number of demand (read+write) miss cycles 276system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 # number of overall miss cycles 277system.cpu.dcache.overall_miss_latency::total 7104361000 # number of overall miss cycles 278system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) 279system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) 280system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 281system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 282system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) 283system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) 284system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 285system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 286system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 287system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 288system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses 289system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses 290system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses 291system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses 292system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 # miss rate for ReadReq accesses 293system.cpu.dcache.ReadReq_miss_rate::total 0.001613 # miss rate for ReadReq accesses 294system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses 295system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses 296system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 # miss rate for SoftPFReq accesses 297system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 # miss rate for SoftPFReq accesses 298system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 # miss rate for demand accesses 299system.cpu.dcache.demand_miss_rate::total 0.003373 # miss rate for demand accesses 300system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 # miss rate for overall accesses 301system.cpu.dcache.overall_miss_rate::total 0.004303 # miss rate for overall accesses 302system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 # average ReadReq miss latency 303system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 # average ReadReq miss latency 304system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 # average WriteReq miss latency 305system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 # average WriteReq miss latency 306system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 # average overall miss latency 307system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 # average overall miss latency 308system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 # average overall miss latency 309system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 # average overall miss latency 310system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 313system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 314system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.cpu.dcache.writebacks::writebacks 127926 # number of writebacks 317system.cpu.dcache.writebacks::total 127926 # number of writebacks 318system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 # number of ReadReq MSHR hits 319system.cpu.dcache.ReadReq_mshr_hits::total 7633 # number of ReadReq MSHR hits 320system.cpu.dcache.demand_mshr_hits::cpu.data 7633 # number of demand (read+write) MSHR hits 321system.cpu.dcache.demand_mshr_hits::total 7633 # number of demand (read+write) MSHR hits 322system.cpu.dcache.overall_mshr_hits::cpu.data 7633 # number of overall MSHR hits 323system.cpu.dcache.overall_mshr_hits::total 7633 # number of overall MSHR hits 324system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses 325system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses 326system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses 327system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses 328system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses 329system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses 330system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses 331system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses 332system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses 333system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses 334system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 # number of ReadReq MSHR miss cycles 335system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 # number of ReadReq MSHR miss cycles 336system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 # number of WriteReq MSHR miss cycles 337system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 # number of WriteReq MSHR miss cycles 338system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 # number of SoftPFReq MSHR miss cycles 339system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 # number of SoftPFReq MSHR miss cycles 340system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 # number of demand (read+write) MSHR miss cycles 341system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 # number of demand (read+write) MSHR miss cycles 342system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 # number of overall MSHR miss cycles 343system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 # number of overall MSHR miss cycles 344system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses 345system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses 346system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 347system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 348system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses 349system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses 350system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses 351system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses 352system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 353system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses 354system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 # average ReadReq mshr miss latency 355system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 # average ReadReq mshr miss latency 356system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency 357system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency 358system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency 359system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency 360system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency 361system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency 362system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency 363system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency 364system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 365system.cpu.icache.tags.replacements 16890 # number of replacements 366system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use 367system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 368system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 369system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 370system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 371system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor 372system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy 373system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy 374system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 375system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 376system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 379system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 380system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses 382system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 383system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 384system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 385system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 386system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 387system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 388system.cpu.icache.overall_hits::total 78126184 # number of overall hits 389system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 390system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 391system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 392system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 393system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 394system.cpu.icache.overall_misses::total 18908 # number of overall misses 395system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 # number of ReadReq miss cycles 396system.cpu.icache.ReadReq_miss_latency::total 429951000 # number of ReadReq miss cycles 397system.cpu.icache.demand_miss_latency::cpu.inst 429951000 # number of demand (read+write) miss cycles 398system.cpu.icache.demand_miss_latency::total 429951000 # number of demand (read+write) miss cycles 399system.cpu.icache.overall_miss_latency::cpu.inst 429951000 # number of overall miss cycles 400system.cpu.icache.overall_miss_latency::total 429951000 # number of overall miss cycles 401system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) 402system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) 403system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses 404system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses 405system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses 406system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses 407system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 408system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 409system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 410system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 411system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 412system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses 413system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 # average ReadReq miss latency 414system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 # average ReadReq miss latency 415system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency 416system.cpu.icache.demand_avg_miss_latency::total 22739.105141 # average overall miss latency 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency 418system.cpu.icache.overall_avg_miss_latency::total 22739.105141 # average overall miss latency 419system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 420system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 424system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.cpu.icache.writebacks::writebacks 16890 # number of writebacks 426system.cpu.icache.writebacks::total 16890 # number of writebacks 427system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 428system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 429system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 430system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 431system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 432system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses 433system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 # number of ReadReq MSHR miss cycles 434system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 # number of ReadReq MSHR miss cycles 435system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 # number of demand (read+write) MSHR miss cycles 436system.cpu.icache.demand_mshr_miss_latency::total 411043000 # number of demand (read+write) MSHR miss cycles 437system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 # number of overall MSHR miss cycles 438system.cpu.icache.overall_mshr_miss_latency::total 411043000 # number of overall MSHR miss cycles 439system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses 440system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses 441system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses 442system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses 443system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 444system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 445system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency 446system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency 447system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency 449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency 450system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency 451system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 452system.cpu.l2cache.tags.replacements 96062 # number of replacements 453system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use 454system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. 455system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. 456system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. 457system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. 458system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor 459system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor 461system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 475system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits 476system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits 477system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 478system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 479system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits 480system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits 481system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits 482system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits 483system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 # number of ReadSharedReq hits 484system.cpu.l2cache.ReadSharedReq_hits::total 31236 # number of ReadSharedReq hits 485system.cpu.l2cache.demand_hits::cpu.inst 15262 # number of demand (read+write) hits 486system.cpu.l2cache.demand_hits::cpu.data 35948 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::total 51210 # number of demand (read+write) hits 488system.cpu.l2cache.overall_hits::cpu.inst 15262 # number of overall hits 489system.cpu.l2cache.overall_hits::cpu.data 35948 # number of overall hits 490system.cpu.l2cache.overall_hits::total 51210 # number of overall hits 491system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 # number of ReadExReq misses 492system.cpu.l2cache.ReadExReq_misses::total 102320 # number of ReadExReq misses 493system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 # number of ReadCleanReq misses 494system.cpu.l2cache.ReadCleanReq_misses::total 3646 # number of ReadCleanReq misses 495system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 # number of ReadSharedReq misses 496system.cpu.l2cache.ReadSharedReq_misses::total 21730 # number of ReadSharedReq misses 497system.cpu.l2cache.demand_misses::cpu.inst 3646 # number of demand (read+write) misses 498system.cpu.l2cache.demand_misses::cpu.data 124050 # number of demand (read+write) misses 499system.cpu.l2cache.demand_misses::total 127696 # number of demand (read+write) misses 500system.cpu.l2cache.overall_misses::cpu.inst 3646 # number of overall misses 501system.cpu.l2cache.overall_misses::cpu.data 124050 # number of overall misses 502system.cpu.l2cache.overall_misses::total 127696 # number of overall misses 503system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 # number of ReadExReq miss cycles 504system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 # number of ReadExReq miss cycles 505system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 # number of ReadCleanReq miss cycles 506system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 # number of ReadCleanReq miss cycles 507system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 # number of ReadSharedReq miss cycles 508system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 # number of ReadSharedReq miss cycles 509system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 # number of demand (read+write) miss cycles 510system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 # number of demand (read+write) miss cycles 511system.cpu.l2cache.demand_miss_latency::total 7728636500 # number of demand (read+write) miss cycles 512system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 # number of overall miss cycles 513system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 # number of overall miss cycles 514system.cpu.l2cache.overall_miss_latency::total 7728636500 # number of overall miss cycles 515system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 # number of WritebackDirty accesses(hits+misses) 516system.cpu.l2cache.WritebackDirty_accesses::total 127926 # number of WritebackDirty accesses(hits+misses) 517system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) 518system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) 519system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) 520system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) 521system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) 522system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) 523system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) 524system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) 525system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses 526system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses 528system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses 531system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 # miss rate for ReadExReq accesses 532system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 # miss rate for ReadExReq accesses 533system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 # miss rate for ReadCleanReq accesses 534system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 # miss rate for ReadCleanReq accesses 535system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 # miss rate for ReadSharedReq accesses 536system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 # miss rate for ReadSharedReq accesses 537system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 # miss rate for demand accesses 538system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 # miss rate for demand accesses 539system.cpu.l2cache.demand_miss_rate::total 0.713760 # miss rate for demand accesses 540system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 # miss rate for overall accesses 541system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 # miss rate for overall accesses 542system.cpu.l2cache.overall_miss_rate::total 0.713760 # miss rate for overall accesses 543system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 # average ReadExReq miss latency 544system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 # average ReadExReq miss latency 545system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 # average ReadCleanReq miss latency 546system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 # average ReadCleanReq miss latency 547system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 # average ReadSharedReq miss latency 548system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 # average ReadSharedReq miss latency 549system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency 550system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency 551system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 # average overall miss latency 552system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 # average overall miss latency 555system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 556system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.l2cache.writebacks::writebacks 86477 # number of writebacks 562system.cpu.l2cache.writebacks::total 86477 # number of writebacks 563system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses 564system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 # number of ReadExReq MSHR misses 566system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 # number of ReadExReq MSHR misses 567system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 # number of ReadCleanReq MSHR misses 568system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 # number of ReadCleanReq MSHR misses 569system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 # number of ReadSharedReq MSHR misses 570system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 # number of ReadSharedReq MSHR misses 571system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 # number of demand (read+write) MSHR misses 572system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 # number of demand (read+write) MSHR misses 573system.cpu.l2cache.demand_mshr_misses::total 127696 # number of demand (read+write) MSHR misses 574system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 # number of overall MSHR misses 575system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 # number of overall MSHR misses 576system.cpu.l2cache.overall_mshr_misses::total 127696 # number of overall MSHR misses 577system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 # number of ReadExReq MSHR miss cycles 578system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 # number of ReadExReq MSHR miss cycles 579system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 # number of ReadCleanReq MSHR miss cycles 580system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 # number of ReadCleanReq MSHR miss cycles 581system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 # number of ReadSharedReq MSHR miss cycles 582system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 # number of ReadSharedReq MSHR miss cycles 583system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 # number of demand (read+write) MSHR miss cycles 584system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 # number of demand (read+write) MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 # number of overall MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 # number of overall MSHR miss cycles 588system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 # number of overall MSHR miss cycles 589system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 590system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 591system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 # mshr miss rate for ReadExReq accesses 592system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 # mshr miss rate for ReadExReq accesses 593system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for ReadCleanReq accesses 594system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 # mshr miss rate for ReadCleanReq accesses 595system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 # mshr miss rate for ReadSharedReq accesses 596system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 # mshr miss rate for ReadSharedReq accesses 597system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for demand accesses 598system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for demand accesses 599system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 # mshr miss rate for demand accesses 600system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for overall accesses 601system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for overall accesses 602system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 # mshr miss rate for overall accesses 603system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 # average ReadExReq mshr miss latency 604system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 # average ReadExReq mshr miss latency 605system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 # average ReadCleanReq mshr miss latency 606system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 # average ReadCleanReq mshr miss latency 607system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 # average ReadSharedReq mshr miss latency 608system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 # average ReadSharedReq mshr miss latency 609system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency 610system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency 611system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency 612system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency 613system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency 614system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency 615system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 616system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 617system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 618system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. 619system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 620system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 621system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 622system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 628system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 629system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution 630system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) 631system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) 632system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) 633system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) 634system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 # Cumulative packet size per connected master and slave (bytes) 635system.cpu.toL2Bus.pkt_size::total 20718208 # Cumulative packet size per connected master and slave (bytes) 636system.cpu.toL2Bus.snoops 96062 # Total snoops (count) 637system.cpu.toL2Bus.snoopTraffic 5534528 # Total snoop traffic (bytes) 638system.cpu.toL2Bus.snoop_fanout::samples 274968 # Request fanout histogram 639system.cpu.toL2Bus.snoop_fanout::mean 0.025367 # Request fanout histogram 640system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 # Request fanout histogram 641system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 642system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% # Request fanout histogram 643system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% # Request fanout histogram 644system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram 645system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 646system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 647system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 648system.cpu.toL2Bus.snoop_fanout::total 274968 # Request fanout histogram 649system.cpu.toL2Bus.reqLayer0.occupancy 320665000 # Layer occupancy (ticks) 650system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 651system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 652system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 653system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 654system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 655system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. 656system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. 657system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 658system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 659system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 660system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 661system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states 662system.membus.trans_dist::ReadResp 25376 # Transaction distribution 663system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution 664system.membus.trans_dist::CleanEvict 6466 # Transaction distribution 665system.membus.trans_dist::ReadExReq 102320 # Transaction distribution 666system.membus.trans_dist::ReadExResp 102320 # Transaction distribution 667system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution 668system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) 670system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 # Cumulative packet size per connected master and slave (bytes) 671system.membus.pkt_size::total 13707072 # Cumulative packet size per connected master and slave (bytes) 672system.membus.snoops 0 # Total snoops (count) 673system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 674system.membus.snoop_fanout::samples 127704 # Request fanout histogram 675system.membus.snoop_fanout::mean 0 # Request fanout histogram 676system.membus.snoop_fanout::stdev 0 # Request fanout histogram 677system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 678system.membus.snoop_fanout::0 127704 100.00% 100.00% # Request fanout histogram 679system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 680system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 681system.membus.snoop_fanout::min_value 0 # Request fanout histogram 682system.membus.snoop_fanout::max_value 0 # Request fanout histogram 683system.membus.snoop_fanout::total 127704 # Request fanout histogram 684system.membus.reqLayer0.occupancy 569386372 # Layer occupancy (ticks) 685system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 686system.membus.respLayer1.occupancy 638480000 # Layer occupancy (ticks) 687system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 688 689---------- End Simulation Statistics ----------