| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 50 51[system.cpu] 52type=TimingSimpleCPU 53children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 54branchPred=Null 55checker=Null 56clk_domain=system.cpu_clk_domain 57cpu_id=0 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 |
| 63default_p_state=UNDEFINED |
|
| 58do_checkpoint_insts=true 59do_quiesce=true 60do_statistics_insts=true 61dstage2_mmu=system.cpu.dstage2_mmu 62dtb=system.cpu.dtb 63eventq_index=0 64function_trace=false 65function_trace_start=0 66interrupts=system.cpu.interrupts 67isa=system.cpu.isa 68istage2_mmu=system.cpu.istage2_mmu 69itb=system.cpu.itb 70max_insts_all_threads=0 71max_insts_any_thread=0 72max_loads_all_threads=0 73max_loads_any_thread=0 74numThreads=1 | 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dstage2_mmu=system.cpu.dstage2_mmu 68dtb=system.cpu.dtb 69eventq_index=0 70function_trace=false 71function_trace_start=0 72interrupts=system.cpu.interrupts 73isa=system.cpu.isa 74istage2_mmu=system.cpu.istage2_mmu 75itb=system.cpu.itb 76max_insts_all_threads=0 77max_insts_any_thread=0 78max_loads_all_threads=0 79max_loads_any_thread=0 80numThreads=1 |
| 81p_state_clk_gate_bins=20 82p_state_clk_gate_max=1000000000000 83p_state_clk_gate_min=1000 84power_model=Null |
|
| 75profile=0 76progress_interval=0 77simpoint_start_insts= 78socket_id=0 79switched_out=false 80system=system 81tracer=system.cpu.tracer 82workload=system.cpu.workload 83dcache_port=system.cpu.dcache.cpu_side 84icache_port=system.cpu.icache.cpu_side 85 86[system.cpu.dcache] 87type=Cache 88children=tags 89addr_ranges=0:18446744073709551615 90assoc=2 91clk_domain=system.cpu_clk_domain 92clusivity=mostly_incl | 85profile=0 86progress_interval=0 87simpoint_start_insts= 88socket_id=0 89switched_out=false 90system=system 91tracer=system.cpu.tracer 92workload=system.cpu.workload 93dcache_port=system.cpu.dcache.cpu_side 94icache_port=system.cpu.icache.cpu_side 95 96[system.cpu.dcache] 97type=Cache 98children=tags 99addr_ranges=0:18446744073709551615 100assoc=2 101clk_domain=system.cpu_clk_domain 102clusivity=mostly_incl |
| 103default_p_state=UNDEFINED |
|
| 93demand_mshr_reserve=1 94eventq_index=0 95hit_latency=2 96is_read_only=false 97max_miss_count=0 98mshrs=4 | 104demand_mshr_reserve=1 105eventq_index=0 106hit_latency=2 107is_read_only=false 108max_miss_count=0 109mshrs=4 |
| 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=1000000000000 112p_state_clk_gate_min=1000 113power_model=Null |
|
| 99prefetch_on_access=false 100prefetcher=Null 101response_latency=2 102sequential_access=false 103size=262144 104system=system 105tags=system.cpu.dcache.tags 106tgts_per_mshr=20 107write_buffers=8 108writeback_clean=false 109cpu_side=system.cpu.dcache_port 110mem_side=system.cpu.toL2Bus.slave[1] 111 112[system.cpu.dcache.tags] 113type=LRU 114assoc=2 115block_size=64 116clk_domain=system.cpu_clk_domain | 114prefetch_on_access=false 115prefetcher=Null 116response_latency=2 117sequential_access=false 118size=262144 119system=system 120tags=system.cpu.dcache.tags 121tgts_per_mshr=20 122write_buffers=8 123writeback_clean=false 124cpu_side=system.cpu.dcache_port 125mem_side=system.cpu.toL2Bus.slave[1] 126 127[system.cpu.dcache.tags] 128type=LRU 129assoc=2 130block_size=64 131clk_domain=system.cpu_clk_domain |
| 132default_p_state=UNDEFINED |
|
| 117eventq_index=0 118hit_latency=2 | 133eventq_index=0 134hit_latency=2 |
| 135p_state_clk_gate_bins=20 136p_state_clk_gate_max=1000000000000 137p_state_clk_gate_min=1000 138power_model=Null |
|
| 119sequential_access=false 120size=262144 121 122[system.cpu.dstage2_mmu] 123type=ArmStage2MMU 124children=stage2_tlb 125eventq_index=0 126stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 133eventq_index=0 134is_stage2=true 135size=32 136walker=system.cpu.dstage2_mmu.stage2_tlb.walker 137 138[system.cpu.dstage2_mmu.stage2_tlb.walker] 139type=ArmTableWalker 140clk_domain=system.cpu_clk_domain | 139sequential_access=false 140size=262144 141 142[system.cpu.dstage2_mmu] 143type=ArmStage2MMU 144children=stage2_tlb 145eventq_index=0 146stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 153eventq_index=0 154is_stage2=true 155size=32 156walker=system.cpu.dstage2_mmu.stage2_tlb.walker 157 158[system.cpu.dstage2_mmu.stage2_tlb.walker] 159type=ArmTableWalker 160clk_domain=system.cpu_clk_domain |
| 161default_p_state=UNDEFINED |
|
| 141eventq_index=0 142is_stage2=true 143num_squash_per_cycle=2 | 162eventq_index=0 163is_stage2=true 164num_squash_per_cycle=2 |
| 165p_state_clk_gate_bins=20 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null |
|
| 144sys=system 145 146[system.cpu.dtb] 147type=ArmTLB 148children=walker 149eventq_index=0 150is_stage2=false 151size=64 152walker=system.cpu.dtb.walker 153 154[system.cpu.dtb.walker] 155type=ArmTableWalker 156clk_domain=system.cpu_clk_domain | 169sys=system 170 171[system.cpu.dtb] 172type=ArmTLB 173children=walker 174eventq_index=0 175is_stage2=false 176size=64 177walker=system.cpu.dtb.walker 178 179[system.cpu.dtb.walker] 180type=ArmTableWalker 181clk_domain=system.cpu_clk_domain |
| 182default_p_state=UNDEFINED |
|
| 157eventq_index=0 158is_stage2=false 159num_squash_per_cycle=2 | 183eventq_index=0 184is_stage2=false 185num_squash_per_cycle=2 |
| 186p_state_clk_gate_bins=20 187p_state_clk_gate_max=1000000000000 188p_state_clk_gate_min=1000 189power_model=Null |
|
| 160sys=system 161port=system.cpu.toL2Bus.slave[3] 162 163[system.cpu.icache] 164type=Cache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=2 168clk_domain=system.cpu_clk_domain 169clusivity=mostly_incl | 190sys=system 191port=system.cpu.toL2Bus.slave[3] 192 193[system.cpu.icache] 194type=Cache 195children=tags 196addr_ranges=0:18446744073709551615 197assoc=2 198clk_domain=system.cpu_clk_domain 199clusivity=mostly_incl |
| 200default_p_state=UNDEFINED |
|
| 170demand_mshr_reserve=1 171eventq_index=0 172hit_latency=2 173is_read_only=true 174max_miss_count=0 175mshrs=4 | 201demand_mshr_reserve=1 202eventq_index=0 203hit_latency=2 204is_read_only=true 205max_miss_count=0 206mshrs=4 |
| 207p_state_clk_gate_bins=20 208p_state_clk_gate_max=1000000000000 209p_state_clk_gate_min=1000 210power_model=Null |
|
| 176prefetch_on_access=false 177prefetcher=Null 178response_latency=2 179sequential_access=false 180size=131072 181system=system 182tags=system.cpu.icache.tags 183tgts_per_mshr=20 184write_buffers=8 185writeback_clean=true 186cpu_side=system.cpu.icache_port 187mem_side=system.cpu.toL2Bus.slave[0] 188 189[system.cpu.icache.tags] 190type=LRU 191assoc=2 192block_size=64 193clk_domain=system.cpu_clk_domain | 211prefetch_on_access=false 212prefetcher=Null 213response_latency=2 214sequential_access=false 215size=131072 216system=system 217tags=system.cpu.icache.tags 218tgts_per_mshr=20 219write_buffers=8 220writeback_clean=true 221cpu_side=system.cpu.icache_port 222mem_side=system.cpu.toL2Bus.slave[0] 223 224[system.cpu.icache.tags] 225type=LRU 226assoc=2 227block_size=64 228clk_domain=system.cpu_clk_domain |
| 229default_p_state=UNDEFINED |
|
| 194eventq_index=0 195hit_latency=2 | 230eventq_index=0 231hit_latency=2 |
| 232p_state_clk_gate_bins=20 233p_state_clk_gate_max=1000000000000 234p_state_clk_gate_min=1000 235power_model=Null |
|
| 196sequential_access=false 197size=131072 198 199[system.cpu.interrupts] 200type=ArmInterrupts 201eventq_index=0 202 203[system.cpu.isa] --- 41 unchanged lines hidden (view full) --- 245eventq_index=0 246is_stage2=true 247size=32 248walker=system.cpu.istage2_mmu.stage2_tlb.walker 249 250[system.cpu.istage2_mmu.stage2_tlb.walker] 251type=ArmTableWalker 252clk_domain=system.cpu_clk_domain | 236sequential_access=false 237size=131072 238 239[system.cpu.interrupts] 240type=ArmInterrupts 241eventq_index=0 242 243[system.cpu.isa] --- 41 unchanged lines hidden (view full) --- 285eventq_index=0 286is_stage2=true 287size=32 288walker=system.cpu.istage2_mmu.stage2_tlb.walker 289 290[system.cpu.istage2_mmu.stage2_tlb.walker] 291type=ArmTableWalker 292clk_domain=system.cpu_clk_domain |
| 293default_p_state=UNDEFINED |
|
| 253eventq_index=0 254is_stage2=true 255num_squash_per_cycle=2 | 294eventq_index=0 295is_stage2=true 296num_squash_per_cycle=2 |
| 297p_state_clk_gate_bins=20 298p_state_clk_gate_max=1000000000000 299p_state_clk_gate_min=1000 300power_model=Null |
|
| 256sys=system 257 258[system.cpu.itb] 259type=ArmTLB 260children=walker 261eventq_index=0 262is_stage2=false 263size=64 264walker=system.cpu.itb.walker 265 266[system.cpu.itb.walker] 267type=ArmTableWalker 268clk_domain=system.cpu_clk_domain | 301sys=system 302 303[system.cpu.itb] 304type=ArmTLB 305children=walker 306eventq_index=0 307is_stage2=false 308size=64 309walker=system.cpu.itb.walker 310 311[system.cpu.itb.walker] 312type=ArmTableWalker 313clk_domain=system.cpu_clk_domain |
| 314default_p_state=UNDEFINED |
|
| 269eventq_index=0 270is_stage2=false 271num_squash_per_cycle=2 | 315eventq_index=0 316is_stage2=false 317num_squash_per_cycle=2 |
| 318p_state_clk_gate_bins=20 319p_state_clk_gate_max=1000000000000 320p_state_clk_gate_min=1000 321power_model=Null |
|
| 272sys=system 273port=system.cpu.toL2Bus.slave[2] 274 275[system.cpu.l2cache] 276type=Cache 277children=tags 278addr_ranges=0:18446744073709551615 279assoc=8 280clk_domain=system.cpu_clk_domain 281clusivity=mostly_incl | 322sys=system 323port=system.cpu.toL2Bus.slave[2] 324 325[system.cpu.l2cache] 326type=Cache 327children=tags 328addr_ranges=0:18446744073709551615 329assoc=8 330clk_domain=system.cpu_clk_domain 331clusivity=mostly_incl |
| 332default_p_state=UNDEFINED |
|
| 282demand_mshr_reserve=1 283eventq_index=0 284hit_latency=20 285is_read_only=false 286max_miss_count=0 287mshrs=20 | 333demand_mshr_reserve=1 334eventq_index=0 335hit_latency=20 336is_read_only=false 337max_miss_count=0 338mshrs=20 |
| 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=1000000000000 341p_state_clk_gate_min=1000 342power_model=Null |
|
| 288prefetch_on_access=false 289prefetcher=Null 290response_latency=20 291sequential_access=false 292size=2097152 293system=system 294tags=system.cpu.l2cache.tags 295tgts_per_mshr=12 296write_buffers=8 297writeback_clean=false 298cpu_side=system.cpu.toL2Bus.master[0] 299mem_side=system.membus.slave[1] 300 301[system.cpu.l2cache.tags] 302type=LRU 303assoc=8 304block_size=64 305clk_domain=system.cpu_clk_domain | 343prefetch_on_access=false 344prefetcher=Null 345response_latency=20 346sequential_access=false 347size=2097152 348system=system 349tags=system.cpu.l2cache.tags 350tgts_per_mshr=12 351write_buffers=8 352writeback_clean=false 353cpu_side=system.cpu.toL2Bus.master[0] 354mem_side=system.membus.slave[1] 355 356[system.cpu.l2cache.tags] 357type=LRU 358assoc=8 359block_size=64 360clk_domain=system.cpu_clk_domain |
| 361default_p_state=UNDEFINED |
|
| 306eventq_index=0 307hit_latency=20 | 362eventq_index=0 363hit_latency=20 |
| 364p_state_clk_gate_bins=20 365p_state_clk_gate_max=1000000000000 366p_state_clk_gate_min=1000 367power_model=Null |
|
| 308sequential_access=false 309size=2097152 310 311[system.cpu.toL2Bus] 312type=CoherentXBar 313children=snoop_filter 314clk_domain=system.cpu_clk_domain | 368sequential_access=false 369size=2097152 370 371[system.cpu.toL2Bus] 372type=CoherentXBar 373children=snoop_filter 374clk_domain=system.cpu_clk_domain |
| 375default_p_state=UNDEFINED |
|
| 315eventq_index=0 316forward_latency=0 317frontend_latency=1 | 376eventq_index=0 377forward_latency=0 378frontend_latency=1 |
| 379p_state_clk_gate_bins=20 380p_state_clk_gate_max=1000000000000 381p_state_clk_gate_min=1000 |
|
| 318point_of_coherency=false | 382point_of_coherency=false |
| 383power_model=Null |
|
| 319response_latency=1 320snoop_filter=system.cpu.toL2Bus.snoop_filter 321snoop_response_latency=1 322system=system 323use_default_range=false 324width=32 325master=system.cpu.l2cache.cpu_side 326slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port --- 14 unchanged lines hidden (view full) --- 341cmd=vortex lendian.raw 342cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing 343drivers= 344egid=100 345env= 346errout=cerr 347euid=100 348eventq_index=0 | 384response_latency=1 385snoop_filter=system.cpu.toL2Bus.snoop_filter 386snoop_response_latency=1 387system=system 388use_default_range=false 389width=32 390master=system.cpu.l2cache.cpu_side 391slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port --- 14 unchanged lines hidden (view full) --- 406cmd=vortex lendian.raw 407cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing 408drivers= 409egid=100 410env= 411errout=cerr 412euid=100 413eventq_index=0 |
| 349executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex | 414executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex |
| 350gid=100 351input=cin 352kvmInSE=false 353max_stack_size=67108864 354output=cout 355pid=100 356ppid=99 357simpoint=0 --- 15 unchanged lines hidden (view full) --- 373enable=false 374eventq_index=0 375sys_clk_domain=system.clk_domain 376transition_latency=100000000 377 378[system.membus] 379type=CoherentXBar 380clk_domain=system.clk_domain | 415gid=100 416input=cin 417kvmInSE=false 418max_stack_size=67108864 419output=cout 420pid=100 421ppid=99 422simpoint=0 --- 15 unchanged lines hidden (view full) --- 438enable=false 439eventq_index=0 440sys_clk_domain=system.clk_domain 441transition_latency=100000000 442 443[system.membus] 444type=CoherentXBar 445clk_domain=system.clk_domain |
| 446default_p_state=UNDEFINED |
|
| 381eventq_index=0 382forward_latency=4 383frontend_latency=3 | 447eventq_index=0 448forward_latency=4 449frontend_latency=3 |
| 450p_state_clk_gate_bins=20 451p_state_clk_gate_max=1000000000000 452p_state_clk_gate_min=1000 |
|
| 384point_of_coherency=true | 453point_of_coherency=true |
| 454power_model=Null |
|
| 385response_latency=2 386snoop_filter=Null 387snoop_response_latency=4 388system=system 389use_default_range=false 390width=16 391master=system.physmem.port 392slave=system.system_port system.cpu.l2cache.mem_side 393 394[system.physmem] 395type=SimpleMemory 396bandwidth=73.000000 397clk_domain=system.clk_domain 398conf_table_reported=true | 455response_latency=2 456snoop_filter=Null 457snoop_response_latency=4 458system=system 459use_default_range=false 460width=16 461master=system.physmem.port 462slave=system.system_port system.cpu.l2cache.mem_side 463 464[system.physmem] 465type=SimpleMemory 466bandwidth=73.000000 467clk_domain=system.clk_domain 468conf_table_reported=true |
| 469default_p_state=UNDEFINED |
|
| 399eventq_index=0 400in_addr_map=true 401latency=30000 402latency_var=0 403null=false | 470eventq_index=0 471in_addr_map=true 472latency=30000 473latency_var=0 474null=false |
| 475p_state_clk_gate_bins=20 476p_state_clk_gate_max=1000000000000 477p_state_clk_gate_min=1000 478power_model=Null |
|
| 404range=0:134217727 405port=system.membus.master[0] 406 407[system.voltage_domain] 408type=VoltageDomain 409eventq_index=0 410voltage=1.000000 411 | 479range=0:134217727 480port=system.membus.master[0] 481 482[system.voltage_domain] 483type=VoltageDomain 484eventq_index=0 485voltage=1.000000 486 |