1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 82 unchanged lines hidden (view full) --- 91tracer=system.cpu.tracer 92workload=system.cpu.workload 93dcache_port=system.cpu.dcache.cpu_side 94icache_port=system.cpu.icache.cpu_side 95 96[system.cpu.dcache] 97type=Cache 98children=tags |
99addr_ranges=0:18446744073709551615:0:0:0:0 |
100assoc=2 101clk_domain=system.cpu_clk_domain 102clusivity=mostly_incl |
103data_latency=2 |
104default_p_state=UNDEFINED 105demand_mshr_reserve=1 106eventq_index=0 |
107is_read_only=false 108max_miss_count=0 109mshrs=4 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=1000000000000 112p_state_clk_gate_min=1000 113power_model=Null 114prefetch_on_access=false 115prefetcher=Null 116response_latency=2 117sequential_access=false 118size=262144 119system=system |
120tag_latency=2 |
121tags=system.cpu.dcache.tags 122tgts_per_mshr=20 123write_buffers=8 124writeback_clean=false 125cpu_side=system.cpu.dcache_port 126mem_side=system.cpu.toL2Bus.slave[1] 127 128[system.cpu.dcache.tags] 129type=LRU 130assoc=2 131block_size=64 132clk_domain=system.cpu_clk_domain |
133data_latency=2 |
134default_p_state=UNDEFINED 135eventq_index=0 |
136p_state_clk_gate_bins=20 137p_state_clk_gate_max=1000000000000 138p_state_clk_gate_min=1000 139power_model=Null 140sequential_access=false 141size=262144 |
142tag_latency=2 |
143 144[system.cpu.dstage2_mmu] 145type=ArmStage2MMU 146children=stage2_tlb 147eventq_index=0 148stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 149sys=system 150tlb=system.cpu.dtb --- 39 unchanged lines hidden (view full) --- 190p_state_clk_gate_min=1000 191power_model=Null 192sys=system 193port=system.cpu.toL2Bus.slave[3] 194 195[system.cpu.icache] 196type=Cache 197children=tags |
198addr_ranges=0:18446744073709551615:0:0:0:0 |
199assoc=2 200clk_domain=system.cpu_clk_domain 201clusivity=mostly_incl |
202data_latency=2 |
203default_p_state=UNDEFINED 204demand_mshr_reserve=1 205eventq_index=0 |
206is_read_only=true 207max_miss_count=0 208mshrs=4 209p_state_clk_gate_bins=20 210p_state_clk_gate_max=1000000000000 211p_state_clk_gate_min=1000 212power_model=Null 213prefetch_on_access=false 214prefetcher=Null 215response_latency=2 216sequential_access=false 217size=131072 218system=system |
219tag_latency=2 |
220tags=system.cpu.icache.tags 221tgts_per_mshr=20 222write_buffers=8 223writeback_clean=true 224cpu_side=system.cpu.icache_port 225mem_side=system.cpu.toL2Bus.slave[0] 226 227[system.cpu.icache.tags] 228type=LRU 229assoc=2 230block_size=64 231clk_domain=system.cpu_clk_domain |
232data_latency=2 |
233default_p_state=UNDEFINED 234eventq_index=0 |
235p_state_clk_gate_bins=20 236p_state_clk_gate_max=1000000000000 237p_state_clk_gate_min=1000 238power_model=Null 239sequential_access=false 240size=131072 |
241tag_latency=2 |
242 243[system.cpu.interrupts] 244type=ArmInterrupts 245eventq_index=0 246 247[system.cpu.isa] 248type=ArmISA 249decoderFlavour=Generic 250eventq_index=0 251fpsid=1090793632 252id_aa64afr0_el1=0 253id_aa64afr1_el1=0 254id_aa64dfr0_el1=1052678 255id_aa64dfr1_el1=0 256id_aa64isar0_el1=0 257id_aa64isar1_el1=0 258id_aa64mmfr0_el1=15728642 259id_aa64mmfr1_el1=0 |
260id_aa64pfr0_el1=34 |
261id_aa64pfr1_el1=0 262id_isar0=34607377 263id_isar1=34677009 264id_isar2=555950401 265id_isar3=17899825 266id_isar4=268501314 267id_isar5=0 268id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 324p_state_clk_gate_min=1000 325power_model=Null 326sys=system 327port=system.cpu.toL2Bus.slave[2] 328 329[system.cpu.l2cache] 330type=Cache 331children=tags |
332addr_ranges=0:18446744073709551615:0:0:0:0 |
333assoc=8 334clk_domain=system.cpu_clk_domain 335clusivity=mostly_incl |
336data_latency=20 |
337default_p_state=UNDEFINED 338demand_mshr_reserve=1 339eventq_index=0 |
340is_read_only=false 341max_miss_count=0 342mshrs=20 343p_state_clk_gate_bins=20 344p_state_clk_gate_max=1000000000000 345p_state_clk_gate_min=1000 346power_model=Null 347prefetch_on_access=false 348prefetcher=Null 349response_latency=20 350sequential_access=false 351size=2097152 352system=system |
353tag_latency=20 |
354tags=system.cpu.l2cache.tags 355tgts_per_mshr=12 356write_buffers=8 357writeback_clean=false 358cpu_side=system.cpu.toL2Bus.master[0] 359mem_side=system.membus.slave[1] 360 361[system.cpu.l2cache.tags] 362type=LRU 363assoc=8 364block_size=64 365clk_domain=system.cpu_clk_domain |
366data_latency=20 |
367default_p_state=UNDEFINED 368eventq_index=0 |
369p_state_clk_gate_bins=20 370p_state_clk_gate_max=1000000000000 371p_state_clk_gate_min=1000 372power_model=Null 373sequential_access=false 374size=2097152 |
375tag_latency=20 |
376 377[system.cpu.toL2Bus] 378type=CoherentXBar 379children=snoop_filter 380clk_domain=system.cpu_clk_domain 381default_p_state=UNDEFINED 382eventq_index=0 383forward_latency=0 --- 28 unchanged lines hidden (view full) --- 412cmd=vortex lendian.raw 413cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing 414drivers= 415egid=100 416env= 417errout=cerr 418euid=100 419eventq_index=0 |
420executable=/dist/m5/cpu2000/binaries/arm/linux/vortex |
421gid=100 422input=cin 423kvmInSE=false 424max_stack_size=67108864 425output=cout 426pid=100 427ppid=99 428simpoint=0 --- 14 unchanged lines hidden (view full) --- 443domains= 444enable=false 445eventq_index=0 446sys_clk_domain=system.clk_domain 447transition_latency=100000000 448 449[system.membus] 450type=CoherentXBar |
451children=snoop_filter |
452clk_domain=system.clk_domain 453default_p_state=UNDEFINED 454eventq_index=0 455forward_latency=4 456frontend_latency=3 457p_state_clk_gate_bins=20 458p_state_clk_gate_max=1000000000000 459p_state_clk_gate_min=1000 460point_of_coherency=true 461power_model=Null 462response_latency=2 |
463snoop_filter=system.membus.snoop_filter |
464snoop_response_latency=4 465system=system 466use_default_range=false 467width=16 468master=system.physmem.port 469slave=system.system_port system.cpu.l2cache.mem_side 470 |
471[system.membus.snoop_filter] 472type=SnoopFilter 473eventq_index=0 474lookup_latency=1 475max_capacity=8388608 476system=system 477 |
478[system.physmem] 479type=SimpleMemory 480bandwidth=73.000000 481clk_domain=system.clk_domain 482conf_table_reported=true 483default_p_state=UNDEFINED 484eventq_index=0 485in_addr_map=true |
486kvm_map=true |
487latency=30000 488latency_var=0 489null=false 490p_state_clk_gate_bins=20 491p_state_clk_gate_max=1000000000000 492p_state_clk_gate_min=1000 493power_model=Null |
494range=0:134217727:0:0:0:0 |
495port=system.membus.master[0] 496 497[system.voltage_domain] 498type=VoltageDomain 499eventq_index=0 500voltage=1.000000 501 |