Cross Reference: /gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini

Deleted Added

sdiff udiff text old ( 11312:3d7a85d71bd1 ) new ( 11388:bd4125134e77 )

full compact

config.ini (11312:3d7a85d71bd1)	config.ini (11388:bd4125134e77)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=TimingSimpleCPU 51children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 52branchPred=Null 53checker=Null 54clk_domain=system.cpu_clk_domain 55cpu_id=0 56do_checkpoint_insts=true 57do_quiesce=true 58do_statistics_insts=true 59dstage2_mmu=system.cpu.dstage2_mmu 60dtb=system.cpu.dtb 61eventq_index=0 62function_trace=false 63function_trace_start=0 64interrupts=system.cpu.interrupts 65isa=system.cpu.isa 66istage2_mmu=system.cpu.istage2_mmu 67itb=system.cpu.itb 68max_insts_all_threads=0 69max_insts_any_thread=0 70max_loads_all_threads=0 71max_loads_any_thread=0 72numThreads=1 73profile=0 74progress_interval=0 75simpoint_start_insts= 76socket_id=0 77switched_out=false 78system=system 79tracer=system.cpu.tracer 80workload=system.cpu.workload 81dcache_port=system.cpu.dcache.cpu_side 82icache_port=system.cpu.icache.cpu_side 83 84[system.cpu.dcache] 85type=Cache 86children=tags 87addr_ranges=0:18446744073709551615 88assoc=2 89clk_domain=system.cpu_clk_domain 90clusivity=mostly_incl 91demand_mshr_reserve=1 92eventq_index=0	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=TimingSimpleCPU 51children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 52branchPred=Null 53checker=Null 54clk_domain=system.cpu_clk_domain 55cpu_id=0 56do_checkpoint_insts=true 57do_quiesce=true 58do_statistics_insts=true 59dstage2_mmu=system.cpu.dstage2_mmu 60dtb=system.cpu.dtb 61eventq_index=0 62function_trace=false 63function_trace_start=0 64interrupts=system.cpu.interrupts 65isa=system.cpu.isa 66istage2_mmu=system.cpu.istage2_mmu 67itb=system.cpu.itb 68max_insts_all_threads=0 69max_insts_any_thread=0 70max_loads_all_threads=0 71max_loads_any_thread=0 72numThreads=1 73profile=0 74progress_interval=0 75simpoint_start_insts= 76socket_id=0 77switched_out=false 78system=system 79tracer=system.cpu.tracer 80workload=system.cpu.workload 81dcache_port=system.cpu.dcache.cpu_side 82icache_port=system.cpu.icache.cpu_side 83 84[system.cpu.dcache] 85type=Cache 86children=tags 87addr_ranges=0:18446744073709551615 88assoc=2 89clk_domain=system.cpu_clk_domain 90clusivity=mostly_incl 91demand_mshr_reserve=1 92eventq_index=0
93forward_snoops=true
94hit_latency=2 95is_read_only=false 96max_miss_count=0 97mshrs=4 98prefetch_on_access=false 99prefetcher=Null 100response_latency=2 101sequential_access=false 102size=262144 103system=system 104tags=system.cpu.dcache.tags 105tgts_per_mshr=20 106write_buffers=8 107writeback_clean=false 108cpu_side=system.cpu.dcache_port 109mem_side=system.cpu.toL2Bus.slave[1] 110 111[system.cpu.dcache.tags] 112type=LRU 113assoc=2 114block_size=64 115clk_domain=system.cpu_clk_domain 116eventq_index=0 117hit_latency=2 118sequential_access=false 119size=262144 120 121[system.cpu.dstage2_mmu] 122type=ArmStage2MMU 123children=stage2_tlb 124eventq_index=0 125stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 126sys=system 127tlb=system.cpu.dtb 128 129[system.cpu.dstage2_mmu.stage2_tlb] 130type=ArmTLB 131children=walker 132eventq_index=0 133is_stage2=true 134size=32 135walker=system.cpu.dstage2_mmu.stage2_tlb.walker 136 137[system.cpu.dstage2_mmu.stage2_tlb.walker] 138type=ArmTableWalker 139clk_domain=system.cpu_clk_domain 140eventq_index=0 141is_stage2=true 142num_squash_per_cycle=2 143sys=system 144 145[system.cpu.dtb] 146type=ArmTLB 147children=walker 148eventq_index=0 149is_stage2=false 150size=64 151walker=system.cpu.dtb.walker 152 153[system.cpu.dtb.walker] 154type=ArmTableWalker 155clk_domain=system.cpu_clk_domain 156eventq_index=0 157is_stage2=false 158num_squash_per_cycle=2 159sys=system 160port=system.cpu.toL2Bus.slave[3] 161 162[system.cpu.icache] 163type=Cache 164children=tags 165addr_ranges=0:18446744073709551615 166assoc=2 167clk_domain=system.cpu_clk_domain 168clusivity=mostly_incl 169demand_mshr_reserve=1 170eventq_index=0	93hit_latency=2 94is_read_only=false 95max_miss_count=0 96mshrs=4 97prefetch_on_access=false 98prefetcher=Null 99response_latency=2 100sequential_access=false 101size=262144 102system=system 103tags=system.cpu.dcache.tags 104tgts_per_mshr=20 105write_buffers=8 106writeback_clean=false 107cpu_side=system.cpu.dcache_port 108mem_side=system.cpu.toL2Bus.slave[1] 109 110[system.cpu.dcache.tags] 111type=LRU 112assoc=2 113block_size=64 114clk_domain=system.cpu_clk_domain 115eventq_index=0 116hit_latency=2 117sequential_access=false 118size=262144 119 120[system.cpu.dstage2_mmu] 121type=ArmStage2MMU 122children=stage2_tlb 123eventq_index=0 124stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 125sys=system 126tlb=system.cpu.dtb 127 128[system.cpu.dstage2_mmu.stage2_tlb] 129type=ArmTLB 130children=walker 131eventq_index=0 132is_stage2=true 133size=32 134walker=system.cpu.dstage2_mmu.stage2_tlb.walker 135 136[system.cpu.dstage2_mmu.stage2_tlb.walker] 137type=ArmTableWalker 138clk_domain=system.cpu_clk_domain 139eventq_index=0 140is_stage2=true 141num_squash_per_cycle=2 142sys=system 143 144[system.cpu.dtb] 145type=ArmTLB 146children=walker 147eventq_index=0 148is_stage2=false 149size=64 150walker=system.cpu.dtb.walker 151 152[system.cpu.dtb.walker] 153type=ArmTableWalker 154clk_domain=system.cpu_clk_domain 155eventq_index=0 156is_stage2=false 157num_squash_per_cycle=2 158sys=system 159port=system.cpu.toL2Bus.slave[3] 160 161[system.cpu.icache] 162type=Cache 163children=tags 164addr_ranges=0:18446744073709551615 165assoc=2 166clk_domain=system.cpu_clk_domain 167clusivity=mostly_incl 168demand_mshr_reserve=1 169eventq_index=0
171forward_snoops=true
172hit_latency=2 173is_read_only=true 174max_miss_count=0 175mshrs=4 176prefetch_on_access=false 177prefetcher=Null 178response_latency=2 179sequential_access=false 180size=131072 181system=system 182tags=system.cpu.icache.tags 183tgts_per_mshr=20 184write_buffers=8 185writeback_clean=true 186cpu_side=system.cpu.icache_port 187mem_side=system.cpu.toL2Bus.slave[0] 188 189[system.cpu.icache.tags] 190type=LRU 191assoc=2 192block_size=64 193clk_domain=system.cpu_clk_domain 194eventq_index=0 195hit_latency=2 196sequential_access=false 197size=131072 198 199[system.cpu.interrupts] 200type=ArmInterrupts 201eventq_index=0 202 203[system.cpu.isa] 204type=ArmISA 205decoderFlavour=Generic 206eventq_index=0 207fpsid=1090793632 208id_aa64afr0_el1=0 209id_aa64afr1_el1=0 210id_aa64dfr0_el1=1052678 211id_aa64dfr1_el1=0 212id_aa64isar0_el1=0 213id_aa64isar1_el1=0 214id_aa64mmfr0_el1=15728642 215id_aa64mmfr1_el1=0 216id_aa64pfr0_el1=17 217id_aa64pfr1_el1=0 218id_isar0=34607377 219id_isar1=34677009 220id_isar2=555950401 221id_isar3=17899825 222id_isar4=268501314 223id_isar5=0 224id_mmfr0=270536963 225id_mmfr1=0 226id_mmfr2=19070976 227id_mmfr3=34611729 228id_pfr0=49 229id_pfr1=4113 230midr=1091551472 231pmu=Null 232system=system 233 234[system.cpu.istage2_mmu] 235type=ArmStage2MMU 236children=stage2_tlb 237eventq_index=0 238stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 239sys=system 240tlb=system.cpu.itb 241 242[system.cpu.istage2_mmu.stage2_tlb] 243type=ArmTLB 244children=walker 245eventq_index=0 246is_stage2=true 247size=32 248walker=system.cpu.istage2_mmu.stage2_tlb.walker 249 250[system.cpu.istage2_mmu.stage2_tlb.walker] 251type=ArmTableWalker 252clk_domain=system.cpu_clk_domain 253eventq_index=0 254is_stage2=true 255num_squash_per_cycle=2 256sys=system 257 258[system.cpu.itb] 259type=ArmTLB 260children=walker 261eventq_index=0 262is_stage2=false 263size=64 264walker=system.cpu.itb.walker 265 266[system.cpu.itb.walker] 267type=ArmTableWalker 268clk_domain=system.cpu_clk_domain 269eventq_index=0 270is_stage2=false 271num_squash_per_cycle=2 272sys=system 273port=system.cpu.toL2Bus.slave[2] 274 275[system.cpu.l2cache] 276type=Cache 277children=tags 278addr_ranges=0:18446744073709551615 279assoc=8 280clk_domain=system.cpu_clk_domain 281clusivity=mostly_incl 282demand_mshr_reserve=1 283eventq_index=0	170hit_latency=2 171is_read_only=true 172max_miss_count=0 173mshrs=4 174prefetch_on_access=false 175prefetcher=Null 176response_latency=2 177sequential_access=false 178size=131072 179system=system 180tags=system.cpu.icache.tags 181tgts_per_mshr=20 182write_buffers=8 183writeback_clean=true 184cpu_side=system.cpu.icache_port 185mem_side=system.cpu.toL2Bus.slave[0] 186 187[system.cpu.icache.tags] 188type=LRU 189assoc=2 190block_size=64 191clk_domain=system.cpu_clk_domain 192eventq_index=0 193hit_latency=2 194sequential_access=false 195size=131072 196 197[system.cpu.interrupts] 198type=ArmInterrupts 199eventq_index=0 200 201[system.cpu.isa] 202type=ArmISA 203decoderFlavour=Generic 204eventq_index=0 205fpsid=1090793632 206id_aa64afr0_el1=0 207id_aa64afr1_el1=0 208id_aa64dfr0_el1=1052678 209id_aa64dfr1_el1=0 210id_aa64isar0_el1=0 211id_aa64isar1_el1=0 212id_aa64mmfr0_el1=15728642 213id_aa64mmfr1_el1=0 214id_aa64pfr0_el1=17 215id_aa64pfr1_el1=0 216id_isar0=34607377 217id_isar1=34677009 218id_isar2=555950401 219id_isar3=17899825 220id_isar4=268501314 221id_isar5=0 222id_mmfr0=270536963 223id_mmfr1=0 224id_mmfr2=19070976 225id_mmfr3=34611729 226id_pfr0=49 227id_pfr1=4113 228midr=1091551472 229pmu=Null 230system=system 231 232[system.cpu.istage2_mmu] 233type=ArmStage2MMU 234children=stage2_tlb 235eventq_index=0 236stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 237sys=system 238tlb=system.cpu.itb 239 240[system.cpu.istage2_mmu.stage2_tlb] 241type=ArmTLB 242children=walker 243eventq_index=0 244is_stage2=true 245size=32 246walker=system.cpu.istage2_mmu.stage2_tlb.walker 247 248[system.cpu.istage2_mmu.stage2_tlb.walker] 249type=ArmTableWalker 250clk_domain=system.cpu_clk_domain 251eventq_index=0 252is_stage2=true 253num_squash_per_cycle=2 254sys=system 255 256[system.cpu.itb] 257type=ArmTLB 258children=walker 259eventq_index=0 260is_stage2=false 261size=64 262walker=system.cpu.itb.walker 263 264[system.cpu.itb.walker] 265type=ArmTableWalker 266clk_domain=system.cpu_clk_domain 267eventq_index=0 268is_stage2=false 269num_squash_per_cycle=2 270sys=system 271port=system.cpu.toL2Bus.slave[2] 272 273[system.cpu.l2cache] 274type=Cache 275children=tags 276addr_ranges=0:18446744073709551615 277assoc=8 278clk_domain=system.cpu_clk_domain 279clusivity=mostly_incl 280demand_mshr_reserve=1 281eventq_index=0
284forward_snoops=true
285hit_latency=20 286is_read_only=false 287max_miss_count=0 288mshrs=20 289prefetch_on_access=false 290prefetcher=Null 291response_latency=20 292sequential_access=false 293size=2097152 294system=system 295tags=system.cpu.l2cache.tags 296tgts_per_mshr=12 297write_buffers=8 298writeback_clean=false 299cpu_side=system.cpu.toL2Bus.master[0] 300mem_side=system.membus.slave[1] 301 302[system.cpu.l2cache.tags] 303type=LRU 304assoc=8 305block_size=64 306clk_domain=system.cpu_clk_domain 307eventq_index=0 308hit_latency=20 309sequential_access=false 310size=2097152 311 312[system.cpu.toL2Bus] 313type=CoherentXBar 314children=snoop_filter 315clk_domain=system.cpu_clk_domain 316eventq_index=0 317forward_latency=0 318frontend_latency=1	282hit_latency=20 283is_read_only=false 284max_miss_count=0 285mshrs=20 286prefetch_on_access=false 287prefetcher=Null 288response_latency=20 289sequential_access=false 290size=2097152 291system=system 292tags=system.cpu.l2cache.tags 293tgts_per_mshr=12 294write_buffers=8 295writeback_clean=false 296cpu_side=system.cpu.toL2Bus.master[0] 297mem_side=system.membus.slave[1] 298 299[system.cpu.l2cache.tags] 300type=LRU 301assoc=8 302block_size=64 303clk_domain=system.cpu_clk_domain 304eventq_index=0 305hit_latency=20 306sequential_access=false 307size=2097152 308 309[system.cpu.toL2Bus] 310type=CoherentXBar 311children=snoop_filter 312clk_domain=system.cpu_clk_domain 313eventq_index=0 314forward_latency=0 315frontend_latency=1
	316point_of_coherency=false
319response_latency=1 320snoop_filter=system.cpu.toL2Bus.snoop_filter 321snoop_response_latency=1 322system=system 323use_default_range=false 324width=32 325master=system.cpu.l2cache.cpu_side 326slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 327 328[system.cpu.toL2Bus.snoop_filter] 329type=SnoopFilter 330eventq_index=0 331lookup_latency=0 332max_capacity=8388608 333system=system 334 335[system.cpu.tracer] 336type=ExeTracer 337eventq_index=0 338 339[system.cpu.workload] 340type=LiveProcess 341cmd=vortex lendian.raw 342cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing 343drivers= 344egid=100 345env= 346errout=cerr 347euid=100 348eventq_index=0	317response_latency=1 318snoop_filter=system.cpu.toL2Bus.snoop_filter 319snoop_response_latency=1 320system=system 321use_default_range=false 322width=32 323master=system.cpu.l2cache.cpu_side 324slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 325 326[system.cpu.toL2Bus.snoop_filter] 327type=SnoopFilter 328eventq_index=0 329lookup_latency=0 330max_capacity=8388608 331system=system 332 333[system.cpu.tracer] 334type=ExeTracer 335eventq_index=0 336 337[system.cpu.workload] 338type=LiveProcess 339cmd=vortex lendian.raw 340cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing 341drivers= 342egid=100 343env= 344errout=cerr 345euid=100 346eventq_index=0
349executable=/dist/m5/cpu2000/binaries/arm/linux/vortex	347executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
350gid=100 351input=cin 352kvmInSE=false 353max_stack_size=67108864 354output=cout 355pid=100 356ppid=99 357simpoint=0 358system=system 359uid=100 360useArchPT=false 361 362[system.cpu_clk_domain] 363type=SrcClockDomain 364clock=500 365domain_id=-1 366eventq_index=0 367init_perf_level=0 368voltage_domain=system.voltage_domain 369 370[system.dvfs_handler] 371type=DVFSHandler 372domains= 373enable=false 374eventq_index=0 375sys_clk_domain=system.clk_domain 376transition_latency=100000000 377 378[system.membus] 379type=CoherentXBar 380clk_domain=system.clk_domain 381eventq_index=0 382forward_latency=4 383frontend_latency=3	348gid=100 349input=cin 350kvmInSE=false 351max_stack_size=67108864 352output=cout 353pid=100 354ppid=99 355simpoint=0 356system=system 357uid=100 358useArchPT=false 359 360[system.cpu_clk_domain] 361type=SrcClockDomain 362clock=500 363domain_id=-1 364eventq_index=0 365init_perf_level=0 366voltage_domain=system.voltage_domain 367 368[system.dvfs_handler] 369type=DVFSHandler 370domains= 371enable=false 372eventq_index=0 373sys_clk_domain=system.clk_domain 374transition_latency=100000000 375 376[system.membus] 377type=CoherentXBar 378clk_domain=system.clk_domain 379eventq_index=0 380forward_latency=4 381frontend_latency=3
	382point_of_coherency=true
384response_latency=2 385snoop_filter=Null 386snoop_response_latency=4 387system=system 388use_default_range=false 389width=16 390master=system.physmem.port 391slave=system.system_port system.cpu.l2cache.mem_side 392 393[system.physmem] 394type=SimpleMemory 395bandwidth=73.000000 396clk_domain=system.clk_domain 397conf_table_reported=true 398eventq_index=0 399in_addr_map=true 400latency=30000 401latency_var=0 402null=false 403range=0:134217727 404port=system.membus.master[0] 405 406[system.voltage_domain] 407type=VoltageDomain 408eventq_index=0 409voltage=1.000000 410	383response_latency=2 384snoop_filter=Null 385snoop_response_latency=4 386system=system 387use_default_range=false 388width=16 389master=system.physmem.port 390slave=system.system_port system.cpu.l2cache.mem_side 391 392[system.physmem] 393type=SimpleMemory 394bandwidth=73.000000 395clk_domain=system.clk_domain 396conf_table_reported=true 397eventq_index=0 398in_addr_map=true 399latency=30000 400latency_var=0 401null=false 402range=0:134217727 403port=system.membus.master[0] 404 405[system.voltage_domain] 406type=VoltageDomain 407eventq_index=0 408voltage=1.000000 409