1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 82 unchanged lines hidden (view full) ---
91tracer=system.cpu.tracer
92workload=system.cpu.workload
93dcache_port=system.cpu.dcache.cpu_side
94icache_port=system.cpu.icache.cpu_side
95
96[system.cpu.dcache]
97type=Cache
98children=tags
99addr_ranges=0:18446744073709551615
100assoc=2
101clk_domain=system.cpu_clk_domain
102clusivity=mostly_incl
103default_p_state=UNDEFINED
104demand_mshr_reserve=1
105eventq_index=0
106hit_latency=2
107is_read_only=false
108max_miss_count=0
109mshrs=4
110p_state_clk_gate_bins=20
111p_state_clk_gate_max=1000000000000
112p_state_clk_gate_min=1000
113power_model=Null
114prefetch_on_access=false
115prefetcher=Null
116response_latency=2
117sequential_access=false
118size=262144
119system=system
120tags=system.cpu.dcache.tags
121tgts_per_mshr=20
122write_buffers=8
123writeback_clean=false
124cpu_side=system.cpu.dcache_port
125mem_side=system.cpu.toL2Bus.slave[1]
126
127[system.cpu.dcache.tags]
128type=LRU
129assoc=2
130block_size=64
131clk_domain=system.cpu_clk_domain
132default_p_state=UNDEFINED
133eventq_index=0
134hit_latency=2
135p_state_clk_gate_bins=20
136p_state_clk_gate_max=1000000000000
137p_state_clk_gate_min=1000
138power_model=Null
139sequential_access=false
140size=262144
141
142[system.cpu.dstage2_mmu]
143type=ArmStage2MMU
144children=stage2_tlb
145eventq_index=0
146stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
147sys=system
148tlb=system.cpu.dtb
--- 39 unchanged lines hidden (view full) ---
188p_state_clk_gate_min=1000
189power_model=Null
190sys=system
191port=system.cpu.toL2Bus.slave[3]
192
193[system.cpu.icache]
194type=Cache
195children=tags
196addr_ranges=0:18446744073709551615
197assoc=2
198clk_domain=system.cpu_clk_domain
199clusivity=mostly_incl
200default_p_state=UNDEFINED
201demand_mshr_reserve=1
202eventq_index=0
203hit_latency=2
204is_read_only=true
205max_miss_count=0
206mshrs=4
207p_state_clk_gate_bins=20
208p_state_clk_gate_max=1000000000000
209p_state_clk_gate_min=1000
210power_model=Null
211prefetch_on_access=false
212prefetcher=Null
213response_latency=2
214sequential_access=false
215size=131072
216system=system
217tags=system.cpu.icache.tags
218tgts_per_mshr=20
219write_buffers=8
220writeback_clean=true
221cpu_side=system.cpu.icache_port
222mem_side=system.cpu.toL2Bus.slave[0]
223
224[system.cpu.icache.tags]
225type=LRU
226assoc=2
227block_size=64
228clk_domain=system.cpu_clk_domain
229default_p_state=UNDEFINED
230eventq_index=0
231hit_latency=2
232p_state_clk_gate_bins=20
233p_state_clk_gate_max=1000000000000
234p_state_clk_gate_min=1000
235power_model=Null
236sequential_access=false
237size=131072
238
239[system.cpu.interrupts]
240type=ArmInterrupts
241eventq_index=0
242
243[system.cpu.isa]
244type=ArmISA
245decoderFlavour=Generic
246eventq_index=0
247fpsid=1090793632
248id_aa64afr0_el1=0
249id_aa64afr1_el1=0
250id_aa64dfr0_el1=1052678
251id_aa64dfr1_el1=0
252id_aa64isar0_el1=0
253id_aa64isar1_el1=0
254id_aa64mmfr0_el1=15728642
255id_aa64mmfr1_el1=0
256id_aa64pfr0_el1=17
257id_aa64pfr1_el1=0
258id_isar0=34607377
259id_isar1=34677009
260id_isar2=555950401
261id_isar3=17899825
262id_isar4=268501314
263id_isar5=0
264id_mmfr0=270536963
--- 55 unchanged lines hidden (view full) ---
320p_state_clk_gate_min=1000
321power_model=Null
322sys=system
323port=system.cpu.toL2Bus.slave[2]
324
325[system.cpu.l2cache]
326type=Cache
327children=tags
328addr_ranges=0:18446744073709551615
329assoc=8
330clk_domain=system.cpu_clk_domain
331clusivity=mostly_incl
332default_p_state=UNDEFINED
333demand_mshr_reserve=1
334eventq_index=0
335hit_latency=20
336is_read_only=false
337max_miss_count=0
338mshrs=20
339p_state_clk_gate_bins=20
340p_state_clk_gate_max=1000000000000
341p_state_clk_gate_min=1000
342power_model=Null
343prefetch_on_access=false
344prefetcher=Null
345response_latency=20
346sequential_access=false
347size=2097152
348system=system
349tags=system.cpu.l2cache.tags
350tgts_per_mshr=12
351write_buffers=8
352writeback_clean=false
353cpu_side=system.cpu.toL2Bus.master[0]
354mem_side=system.membus.slave[1]
355
356[system.cpu.l2cache.tags]
357type=LRU
358assoc=8
359block_size=64
360clk_domain=system.cpu_clk_domain
361default_p_state=UNDEFINED
362eventq_index=0
363hit_latency=20
364p_state_clk_gate_bins=20
365p_state_clk_gate_max=1000000000000
366p_state_clk_gate_min=1000
367power_model=Null
368sequential_access=false
369size=2097152
370
371[system.cpu.toL2Bus]
372type=CoherentXBar
373children=snoop_filter
374clk_domain=system.cpu_clk_domain
375default_p_state=UNDEFINED
376eventq_index=0
377forward_latency=0
--- 28 unchanged lines hidden (view full) ---
406cmd=vortex lendian.raw
407cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
408drivers=
409egid=100
410env=
411errout=cerr
412euid=100
413eventq_index=0
414executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
415gid=100
416input=cin
417kvmInSE=false
418max_stack_size=67108864
419output=cout
420pid=100
421ppid=99
422simpoint=0
--- 14 unchanged lines hidden (view full) ---
437domains=
438enable=false
439eventq_index=0
440sys_clk_domain=system.clk_domain
441transition_latency=100000000
442
443[system.membus]
444type=CoherentXBar
445clk_domain=system.clk_domain
446default_p_state=UNDEFINED
447eventq_index=0
448forward_latency=4
449frontend_latency=3
450p_state_clk_gate_bins=20
451p_state_clk_gate_max=1000000000000
452p_state_clk_gate_min=1000
453point_of_coherency=true
454power_model=Null
455response_latency=2
456snoop_filter=Null
457snoop_response_latency=4
458system=system
459use_default_range=false
460width=16
461master=system.physmem.port
462slave=system.system_port system.cpu.l2cache.mem_side
463
464[system.physmem]
465type=SimpleMemory
466bandwidth=73.000000
467clk_domain=system.clk_domain
468conf_table_reported=true
469default_p_state=UNDEFINED
470eventq_index=0
471in_addr_map=true
472latency=30000
473latency_var=0
474null=false
475p_state_clk_gate_bins=20
476p_state_clk_gate_max=1000000000000
477p_state_clk_gate_min=1000
478power_model=Null
479range=0:134217727
480port=system.membus.master[0]
481
482[system.voltage_domain]
483type=VoltageDomain
484eventq_index=0
485voltage=1.000000
486
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 82 unchanged lines hidden (view full) ---
91tracer=system.cpu.tracer
92workload=system.cpu.workload
93dcache_port=system.cpu.dcache.cpu_side
94icache_port=system.cpu.icache.cpu_side
95
96[system.cpu.dcache]
97type=Cache
98children=tags
99addr_ranges=0:18446744073709551615
100assoc=2
101clk_domain=system.cpu_clk_domain
102clusivity=mostly_incl
103default_p_state=UNDEFINED
104demand_mshr_reserve=1
105eventq_index=0
106hit_latency=2
107is_read_only=false
108max_miss_count=0
109mshrs=4
110p_state_clk_gate_bins=20
111p_state_clk_gate_max=1000000000000
112p_state_clk_gate_min=1000
113power_model=Null
114prefetch_on_access=false
115prefetcher=Null
116response_latency=2
117sequential_access=false
118size=262144
119system=system
120tags=system.cpu.dcache.tags
121tgts_per_mshr=20
122write_buffers=8
123writeback_clean=false
124cpu_side=system.cpu.dcache_port
125mem_side=system.cpu.toL2Bus.slave[1]
126
127[system.cpu.dcache.tags]
128type=LRU
129assoc=2
130block_size=64
131clk_domain=system.cpu_clk_domain
132default_p_state=UNDEFINED
133eventq_index=0
134hit_latency=2
135p_state_clk_gate_bins=20
136p_state_clk_gate_max=1000000000000
137p_state_clk_gate_min=1000
138power_model=Null
139sequential_access=false
140size=262144
141
142[system.cpu.dstage2_mmu]
143type=ArmStage2MMU
144children=stage2_tlb
145eventq_index=0
146stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
147sys=system
148tlb=system.cpu.dtb
--- 39 unchanged lines hidden (view full) ---
188p_state_clk_gate_min=1000
189power_model=Null
190sys=system
191port=system.cpu.toL2Bus.slave[3]
192
193[system.cpu.icache]
194type=Cache
195children=tags
196addr_ranges=0:18446744073709551615
197assoc=2
198clk_domain=system.cpu_clk_domain
199clusivity=mostly_incl
200default_p_state=UNDEFINED
201demand_mshr_reserve=1
202eventq_index=0
203hit_latency=2
204is_read_only=true
205max_miss_count=0
206mshrs=4
207p_state_clk_gate_bins=20
208p_state_clk_gate_max=1000000000000
209p_state_clk_gate_min=1000
210power_model=Null
211prefetch_on_access=false
212prefetcher=Null
213response_latency=2
214sequential_access=false
215size=131072
216system=system
217tags=system.cpu.icache.tags
218tgts_per_mshr=20
219write_buffers=8
220writeback_clean=true
221cpu_side=system.cpu.icache_port
222mem_side=system.cpu.toL2Bus.slave[0]
223
224[system.cpu.icache.tags]
225type=LRU
226assoc=2
227block_size=64
228clk_domain=system.cpu_clk_domain
229default_p_state=UNDEFINED
230eventq_index=0
231hit_latency=2
232p_state_clk_gate_bins=20
233p_state_clk_gate_max=1000000000000
234p_state_clk_gate_min=1000
235power_model=Null
236sequential_access=false
237size=131072
238
239[system.cpu.interrupts]
240type=ArmInterrupts
241eventq_index=0
242
243[system.cpu.isa]
244type=ArmISA
245decoderFlavour=Generic
246eventq_index=0
247fpsid=1090793632
248id_aa64afr0_el1=0
249id_aa64afr1_el1=0
250id_aa64dfr0_el1=1052678
251id_aa64dfr1_el1=0
252id_aa64isar0_el1=0
253id_aa64isar1_el1=0
254id_aa64mmfr0_el1=15728642
255id_aa64mmfr1_el1=0
256id_aa64pfr0_el1=17
257id_aa64pfr1_el1=0
258id_isar0=34607377
259id_isar1=34677009
260id_isar2=555950401
261id_isar3=17899825
262id_isar4=268501314
263id_isar5=0
264id_mmfr0=270536963
--- 55 unchanged lines hidden (view full) ---
320p_state_clk_gate_min=1000
321power_model=Null
322sys=system
323port=system.cpu.toL2Bus.slave[2]
324
325[system.cpu.l2cache]
326type=Cache
327children=tags
328addr_ranges=0:18446744073709551615
329assoc=8
330clk_domain=system.cpu_clk_domain
331clusivity=mostly_incl
332default_p_state=UNDEFINED
333demand_mshr_reserve=1
334eventq_index=0
335hit_latency=20
336is_read_only=false
337max_miss_count=0
338mshrs=20
339p_state_clk_gate_bins=20
340p_state_clk_gate_max=1000000000000
341p_state_clk_gate_min=1000
342power_model=Null
343prefetch_on_access=false
344prefetcher=Null
345response_latency=20
346sequential_access=false
347size=2097152
348system=system
349tags=system.cpu.l2cache.tags
350tgts_per_mshr=12
351write_buffers=8
352writeback_clean=false
353cpu_side=system.cpu.toL2Bus.master[0]
354mem_side=system.membus.slave[1]
355
356[system.cpu.l2cache.tags]
357type=LRU
358assoc=8
359block_size=64
360clk_domain=system.cpu_clk_domain
361default_p_state=UNDEFINED
362eventq_index=0
363hit_latency=20
364p_state_clk_gate_bins=20
365p_state_clk_gate_max=1000000000000
366p_state_clk_gate_min=1000
367power_model=Null
368sequential_access=false
369size=2097152
370
371[system.cpu.toL2Bus]
372type=CoherentXBar
373children=snoop_filter
374clk_domain=system.cpu_clk_domain
375default_p_state=UNDEFINED
376eventq_index=0
377forward_latency=0
--- 28 unchanged lines hidden (view full) ---
406cmd=vortex lendian.raw
407cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
408drivers=
409egid=100
410env=
411errout=cerr
412euid=100
413eventq_index=0
414executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
415gid=100
416input=cin
417kvmInSE=false
418max_stack_size=67108864
419output=cout
420pid=100
421ppid=99
422simpoint=0
--- 14 unchanged lines hidden (view full) ---
437domains=
438enable=false
439eventq_index=0
440sys_clk_domain=system.clk_domain
441transition_latency=100000000
442
443[system.membus]
444type=CoherentXBar
445clk_domain=system.clk_domain
446default_p_state=UNDEFINED
447eventq_index=0
448forward_latency=4
449frontend_latency=3
450p_state_clk_gate_bins=20
451p_state_clk_gate_max=1000000000000
452p_state_clk_gate_min=1000
453point_of_coherency=true
454power_model=Null
455response_latency=2
456snoop_filter=Null
457snoop_response_latency=4
458system=system
459use_default_range=false
460width=16
461master=system.physmem.port
462slave=system.system_port system.cpu.l2cache.mem_side
463
464[system.physmem]
465type=SimpleMemory
466bandwidth=73.000000
467clk_domain=system.clk_domain
468conf_table_reported=true
469default_p_state=UNDEFINED
470eventq_index=0
471in_addr_map=true
472latency=30000
473latency_var=0
474null=false
475p_state_clk_gate_bins=20
476p_state_clk_gate_max=1000000000000
477p_state_clk_gate_min=1000
478power_model=Null
479range=0:134217727
480port=system.membus.master[0]
481
482[system.voltage_domain]
483type=VoltageDomain
484eventq_index=0
485voltage=1.000000
486