1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 76 unchanged lines hidden (view full) ---
85type=Cache
86children=tags
87addr_ranges=0:18446744073709551615
88assoc=2
89clk_domain=system.cpu_clk_domain
90clusivity=mostly_incl
91demand_mshr_reserve=1
92eventq_index=0
93forward_snoops=true
94hit_latency=2
95is_read_only=false
96max_miss_count=0
97mshrs=4
98prefetch_on_access=false
99prefetcher=Null
100response_latency=2
101sequential_access=false
--- 61 unchanged lines hidden (view full) ---
163type=Cache
164children=tags
165addr_ranges=0:18446744073709551615
166assoc=2
167clk_domain=system.cpu_clk_domain
168clusivity=mostly_incl
169demand_mshr_reserve=1
170eventq_index=0
171forward_snoops=true
172hit_latency=2
173is_read_only=true
174max_miss_count=0
175mshrs=4
176prefetch_on_access=false
177prefetcher=Null
178response_latency=2
179sequential_access=false
--- 96 unchanged lines hidden (view full) ---
276type=Cache
277children=tags
278addr_ranges=0:18446744073709551615
279assoc=8
280clk_domain=system.cpu_clk_domain
281clusivity=mostly_incl
282demand_mshr_reserve=1
283eventq_index=0
284forward_snoops=true
285hit_latency=20
286is_read_only=false
287max_miss_count=0
288mshrs=20
289prefetch_on_access=false
290prefetcher=Null
291response_latency=20
292sequential_access=false
--- 18 unchanged lines hidden (view full) ---
311
312[system.cpu.toL2Bus]
313type=CoherentXBar
314children=snoop_filter
315clk_domain=system.cpu_clk_domain
316eventq_index=0
317forward_latency=0
318frontend_latency=1
319response_latency=1
320snoop_filter=system.cpu.toL2Bus.snoop_filter
321snoop_response_latency=1
322system=system
323use_default_range=false
324width=32
325master=system.cpu.l2cache.cpu_side
326slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
--- 14 unchanged lines hidden (view full) ---
341cmd=vortex lendian.raw
342cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
343drivers=
344egid=100
345env=
346errout=cerr
347euid=100
348eventq_index=0
349executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
350gid=100
351input=cin
352kvmInSE=false
353max_stack_size=67108864
354output=cout
355pid=100
356ppid=99
357simpoint=0
--- 18 unchanged lines hidden (view full) ---
376transition_latency=100000000
377
378[system.membus]
379type=CoherentXBar
380clk_domain=system.clk_domain
381eventq_index=0
382forward_latency=4
383frontend_latency=3
384response_latency=2
385snoop_filter=Null
386snoop_response_latency=4
387system=system
388use_default_range=false
389width=16
390master=system.physmem.port
391slave=system.system_port system.cpu.l2cache.mem_side
--- 19 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 76 unchanged lines hidden (view full) ---
85type=Cache
86children=tags
87addr_ranges=0:18446744073709551615
88assoc=2
89clk_domain=system.cpu_clk_domain
90clusivity=mostly_incl
91demand_mshr_reserve=1
92eventq_index=0
93forward_snoops=true
94hit_latency=2
95is_read_only=false
96max_miss_count=0
97mshrs=4
98prefetch_on_access=false
99prefetcher=Null
100response_latency=2
101sequential_access=false
--- 61 unchanged lines hidden (view full) ---
163type=Cache
164children=tags
165addr_ranges=0:18446744073709551615
166assoc=2
167clk_domain=system.cpu_clk_domain
168clusivity=mostly_incl
169demand_mshr_reserve=1
170eventq_index=0
171forward_snoops=true
172hit_latency=2
173is_read_only=true
174max_miss_count=0
175mshrs=4
176prefetch_on_access=false
177prefetcher=Null
178response_latency=2
179sequential_access=false
--- 96 unchanged lines hidden (view full) ---
276type=Cache
277children=tags
278addr_ranges=0:18446744073709551615
279assoc=8
280clk_domain=system.cpu_clk_domain
281clusivity=mostly_incl
282demand_mshr_reserve=1
283eventq_index=0
284forward_snoops=true
285hit_latency=20
286is_read_only=false
287max_miss_count=0
288mshrs=20
289prefetch_on_access=false
290prefetcher=Null
291response_latency=20
292sequential_access=false
--- 18 unchanged lines hidden (view full) ---
311
312[system.cpu.toL2Bus]
313type=CoherentXBar
314children=snoop_filter
315clk_domain=system.cpu_clk_domain
316eventq_index=0
317forward_latency=0
318frontend_latency=1
319response_latency=1
320snoop_filter=system.cpu.toL2Bus.snoop_filter
321snoop_response_latency=1
322system=system
323use_default_range=false
324width=32
325master=system.cpu.l2cache.cpu_side
326slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
--- 14 unchanged lines hidden (view full) ---
341cmd=vortex lendian.raw
342cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
343drivers=
344egid=100
345env=
346errout=cerr
347euid=100
348eventq_index=0
349executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
350gid=100
351input=cin
352kvmInSE=false
353max_stack_size=67108864
354output=cout
355pid=100
356ppid=99
357simpoint=0
--- 18 unchanged lines hidden (view full) ---
376transition_latency=100000000
377
378[system.membus]
379type=CoherentXBar
380clk_domain=system.clk_domain
381eventq_index=0
382forward_latency=4
383frontend_latency=3
384response_latency=2
385snoop_filter=Null
386snoop_response_latency=4
387system=system
388use_default_range=false
389width=16
390master=system.physmem.port
391slave=system.system_port system.cpu.l2cache.mem_side
--- 19 unchanged lines hidden ---