1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 76 unchanged lines hidden (view full) ---
85type=Cache
86children=tags
87addr_ranges=0:18446744073709551615
88assoc=2
89clk_domain=system.cpu_clk_domain
90clusivity=mostly_incl
91demand_mshr_reserve=1
92eventq_index=0
93hit_latency=2
94is_read_only=false
95max_miss_count=0
96mshrs=4
97prefetch_on_access=false
98prefetcher=Null
99response_latency=2
100sequential_access=false
--- 61 unchanged lines hidden (view full) ---
162type=Cache
163children=tags
164addr_ranges=0:18446744073709551615
165assoc=2
166clk_domain=system.cpu_clk_domain
167clusivity=mostly_incl
168demand_mshr_reserve=1
169eventq_index=0
170hit_latency=2
171is_read_only=true
172max_miss_count=0
173mshrs=4
174prefetch_on_access=false
175prefetcher=Null
176response_latency=2
177sequential_access=false
--- 96 unchanged lines hidden (view full) ---
274type=Cache
275children=tags
276addr_ranges=0:18446744073709551615
277assoc=8
278clk_domain=system.cpu_clk_domain
279clusivity=mostly_incl
280demand_mshr_reserve=1
281eventq_index=0
282hit_latency=20
283is_read_only=false
284max_miss_count=0
285mshrs=20
286prefetch_on_access=false
287prefetcher=Null
288response_latency=20
289sequential_access=false
--- 18 unchanged lines hidden (view full) ---
308
309[system.cpu.toL2Bus]
310type=CoherentXBar
311children=snoop_filter
312clk_domain=system.cpu_clk_domain
313eventq_index=0
314forward_latency=0
315frontend_latency=1
316point_of_coherency=false
317response_latency=1
318snoop_filter=system.cpu.toL2Bus.snoop_filter
319snoop_response_latency=1
320system=system
321use_default_range=false
322width=32
323master=system.cpu.l2cache.cpu_side
324slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
--- 14 unchanged lines hidden (view full) ---
339cmd=vortex lendian.raw
340cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
341drivers=
342egid=100
343env=
344errout=cerr
345euid=100
346eventq_index=0
347executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
348gid=100
349input=cin
350kvmInSE=false
351max_stack_size=67108864
352output=cout
353pid=100
354ppid=99
355simpoint=0
--- 18 unchanged lines hidden (view full) ---
374transition_latency=100000000
375
376[system.membus]
377type=CoherentXBar
378clk_domain=system.clk_domain
379eventq_index=0
380forward_latency=4
381frontend_latency=3
382point_of_coherency=true
383response_latency=2
384snoop_filter=Null
385snoop_response_latency=4
386system=system
387use_default_range=false
388width=16
389master=system.physmem.port
390slave=system.system_port system.cpu.l2cache.mem_side
--- 19 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 76 unchanged lines hidden (view full) ---
85type=Cache
86children=tags
87addr_ranges=0:18446744073709551615
88assoc=2
89clk_domain=system.cpu_clk_domain
90clusivity=mostly_incl
91demand_mshr_reserve=1
92eventq_index=0
93hit_latency=2
94is_read_only=false
95max_miss_count=0
96mshrs=4
97prefetch_on_access=false
98prefetcher=Null
99response_latency=2
100sequential_access=false
--- 61 unchanged lines hidden (view full) ---
162type=Cache
163children=tags
164addr_ranges=0:18446744073709551615
165assoc=2
166clk_domain=system.cpu_clk_domain
167clusivity=mostly_incl
168demand_mshr_reserve=1
169eventq_index=0
170hit_latency=2
171is_read_only=true
172max_miss_count=0
173mshrs=4
174prefetch_on_access=false
175prefetcher=Null
176response_latency=2
177sequential_access=false
--- 96 unchanged lines hidden (view full) ---
274type=Cache
275children=tags
276addr_ranges=0:18446744073709551615
277assoc=8
278clk_domain=system.cpu_clk_domain
279clusivity=mostly_incl
280demand_mshr_reserve=1
281eventq_index=0
282hit_latency=20
283is_read_only=false
284max_miss_count=0
285mshrs=20
286prefetch_on_access=false
287prefetcher=Null
288response_latency=20
289sequential_access=false
--- 18 unchanged lines hidden (view full) ---
308
309[system.cpu.toL2Bus]
310type=CoherentXBar
311children=snoop_filter
312clk_domain=system.cpu_clk_domain
313eventq_index=0
314forward_latency=0
315frontend_latency=1
316point_of_coherency=false
317response_latency=1
318snoop_filter=system.cpu.toL2Bus.snoop_filter
319snoop_response_latency=1
320system=system
321use_default_range=false
322width=32
323master=system.cpu.l2cache.cpu_side
324slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
--- 14 unchanged lines hidden (view full) ---
339cmd=vortex lendian.raw
340cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
341drivers=
342egid=100
343env=
344errout=cerr
345euid=100
346eventq_index=0
347executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
348gid=100
349input=cin
350kvmInSE=false
351max_stack_size=67108864
352output=cout
353pid=100
354ppid=99
355simpoint=0
--- 18 unchanged lines hidden (view full) ---
374transition_latency=100000000
375
376[system.membus]
377type=CoherentXBar
378clk_domain=system.clk_domain
379eventq_index=0
380forward_latency=4
381frontend_latency=3
382point_of_coherency=true
383response_latency=2
384snoop_filter=Null
385snoop_response_latency=4
386system=system
387use_default_range=false
388width=16
389master=system.physmem.port
390slave=system.system_port system.cpu.l2cache.mem_side
--- 19 unchanged lines hidden ---