| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=atomic 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=atomic 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 50 51[system.cpu] 52type=AtomicSimpleCPU 53children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload 54branchPred=Null 55checker=Null 56clk_domain=system.cpu_clk_domain 57cpu_id=0 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 55 56[system.cpu] 57type=AtomicSimpleCPU 58children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 |
| 63default_p_state=UNDEFINED |
|
| 58do_checkpoint_insts=true 59do_quiesce=true 60do_statistics_insts=true 61dstage2_mmu=system.cpu.dstage2_mmu 62dtb=system.cpu.dtb 63eventq_index=0 64fastmem=false 65function_trace=false 66function_trace_start=0 67interrupts=system.cpu.interrupts 68isa=system.cpu.isa 69istage2_mmu=system.cpu.istage2_mmu 70itb=system.cpu.itb 71max_insts_all_threads=0 72max_insts_any_thread=0 73max_loads_all_threads=0 74max_loads_any_thread=0 75numThreads=1 | 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dstage2_mmu=system.cpu.dstage2_mmu 68dtb=system.cpu.dtb 69eventq_index=0 70fastmem=false 71function_trace=false 72function_trace_start=0 73interrupts=system.cpu.interrupts 74isa=system.cpu.isa 75istage2_mmu=system.cpu.istage2_mmu 76itb=system.cpu.itb 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81numThreads=1 |
| 82p_state_clk_gate_bins=20 83p_state_clk_gate_max=1000000000000 84p_state_clk_gate_min=1000 85power_model=Null |
|
| 76profile=0 77progress_interval=0 78simpoint_start_insts= 79simulate_data_stalls=false 80simulate_inst_stalls=false 81socket_id=0 82switched_out=false 83system=system --- 17 unchanged lines hidden (view full) --- 101eventq_index=0 102is_stage2=true 103size=32 104walker=system.cpu.dstage2_mmu.stage2_tlb.walker 105 106[system.cpu.dstage2_mmu.stage2_tlb.walker] 107type=ArmTableWalker 108clk_domain=system.cpu_clk_domain | 86profile=0 87progress_interval=0 88simpoint_start_insts= 89simulate_data_stalls=false 90simulate_inst_stalls=false 91socket_id=0 92switched_out=false 93system=system --- 17 unchanged lines hidden (view full) --- 111eventq_index=0 112is_stage2=true 113size=32 114walker=system.cpu.dstage2_mmu.stage2_tlb.walker 115 116[system.cpu.dstage2_mmu.stage2_tlb.walker] 117type=ArmTableWalker 118clk_domain=system.cpu_clk_domain |
| 119default_p_state=UNDEFINED |
|
| 109eventq_index=0 110is_stage2=true 111num_squash_per_cycle=2 | 120eventq_index=0 121is_stage2=true 122num_squash_per_cycle=2 |
| 123p_state_clk_gate_bins=20 124p_state_clk_gate_max=1000000000000 125p_state_clk_gate_min=1000 126power_model=Null |
|
| 112sys=system 113 114[system.cpu.dtb] 115type=ArmTLB 116children=walker 117eventq_index=0 118is_stage2=false 119size=64 120walker=system.cpu.dtb.walker 121 122[system.cpu.dtb.walker] 123type=ArmTableWalker 124clk_domain=system.cpu_clk_domain | 127sys=system 128 129[system.cpu.dtb] 130type=ArmTLB 131children=walker 132eventq_index=0 133is_stage2=false 134size=64 135walker=system.cpu.dtb.walker 136 137[system.cpu.dtb.walker] 138type=ArmTableWalker 139clk_domain=system.cpu_clk_domain |
| 140default_p_state=UNDEFINED |
|
| 125eventq_index=0 126is_stage2=false 127num_squash_per_cycle=2 | 141eventq_index=0 142is_stage2=false 143num_squash_per_cycle=2 |
| 144p_state_clk_gate_bins=20 145p_state_clk_gate_max=1000000000000 146p_state_clk_gate_min=1000 147power_model=Null |
|
| 128sys=system 129port=system.membus.slave[4] 130 131[system.cpu.interrupts] 132type=ArmInterrupts 133eventq_index=0 134 135[system.cpu.isa] --- 41 unchanged lines hidden (view full) --- 177eventq_index=0 178is_stage2=true 179size=32 180walker=system.cpu.istage2_mmu.stage2_tlb.walker 181 182[system.cpu.istage2_mmu.stage2_tlb.walker] 183type=ArmTableWalker 184clk_domain=system.cpu_clk_domain | 148sys=system 149port=system.membus.slave[4] 150 151[system.cpu.interrupts] 152type=ArmInterrupts 153eventq_index=0 154 155[system.cpu.isa] --- 41 unchanged lines hidden (view full) --- 197eventq_index=0 198is_stage2=true 199size=32 200walker=system.cpu.istage2_mmu.stage2_tlb.walker 201 202[system.cpu.istage2_mmu.stage2_tlb.walker] 203type=ArmTableWalker 204clk_domain=system.cpu_clk_domain |
| 205default_p_state=UNDEFINED |
|
| 185eventq_index=0 186is_stage2=true 187num_squash_per_cycle=2 | 206eventq_index=0 207is_stage2=true 208num_squash_per_cycle=2 |
| 209p_state_clk_gate_bins=20 210p_state_clk_gate_max=1000000000000 211p_state_clk_gate_min=1000 212power_model=Null |
|
| 188sys=system 189 190[system.cpu.itb] 191type=ArmTLB 192children=walker 193eventq_index=0 194is_stage2=false 195size=64 196walker=system.cpu.itb.walker 197 198[system.cpu.itb.walker] 199type=ArmTableWalker 200clk_domain=system.cpu_clk_domain | 213sys=system 214 215[system.cpu.itb] 216type=ArmTLB 217children=walker 218eventq_index=0 219is_stage2=false 220size=64 221walker=system.cpu.itb.walker 222 223[system.cpu.itb.walker] 224type=ArmTableWalker 225clk_domain=system.cpu_clk_domain |
| 226default_p_state=UNDEFINED |
|
| 201eventq_index=0 202is_stage2=false 203num_squash_per_cycle=2 | 227eventq_index=0 228is_stage2=false 229num_squash_per_cycle=2 |
| 230p_state_clk_gate_bins=20 231p_state_clk_gate_max=1000000000000 232p_state_clk_gate_min=1000 233power_model=Null |
|
| 204sys=system 205port=system.membus.slave[3] 206 207[system.cpu.tracer] 208type=ExeTracer 209eventq_index=0 210 211[system.cpu.workload] 212type=LiveProcess 213cmd=vortex lendian.raw 214cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic 215drivers= 216egid=100 217env= 218errout=cerr 219euid=100 220eventq_index=0 | 234sys=system 235port=system.membus.slave[3] 236 237[system.cpu.tracer] 238type=ExeTracer 239eventq_index=0 240 241[system.cpu.workload] 242type=LiveProcess 243cmd=vortex lendian.raw 244cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic 245drivers= 246egid=100 247env= 248errout=cerr 249euid=100 250eventq_index=0 |
| 221executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex | 251executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex |
| 222gid=100 223input=cin 224kvmInSE=false 225max_stack_size=67108864 226output=cout 227pid=100 228ppid=99 229simpoint=0 --- 15 unchanged lines hidden (view full) --- 245enable=false 246eventq_index=0 247sys_clk_domain=system.clk_domain 248transition_latency=100000000 249 250[system.membus] 251type=CoherentXBar 252clk_domain=system.clk_domain | 252gid=100 253input=cin 254kvmInSE=false 255max_stack_size=67108864 256output=cout 257pid=100 258ppid=99 259simpoint=0 --- 15 unchanged lines hidden (view full) --- 275enable=false 276eventq_index=0 277sys_clk_domain=system.clk_domain 278transition_latency=100000000 279 280[system.membus] 281type=CoherentXBar 282clk_domain=system.clk_domain |
| 283default_p_state=UNDEFINED |
|
| 253eventq_index=0 254forward_latency=4 255frontend_latency=3 | 284eventq_index=0 285forward_latency=4 286frontend_latency=3 |
| 287p_state_clk_gate_bins=20 288p_state_clk_gate_max=1000000000000 289p_state_clk_gate_min=1000 |
|
| 256point_of_coherency=true | 290point_of_coherency=true |
| 291power_model=Null |
|
| 257response_latency=2 258snoop_filter=Null 259snoop_response_latency=4 260system=system 261use_default_range=false 262width=16 263master=system.physmem.port 264slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port 265 266[system.physmem] 267type=SimpleMemory 268bandwidth=73.000000 269clk_domain=system.clk_domain 270conf_table_reported=true | 292response_latency=2 293snoop_filter=Null 294snoop_response_latency=4 295system=system 296use_default_range=false 297width=16 298master=system.physmem.port 299slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port 300 301[system.physmem] 302type=SimpleMemory 303bandwidth=73.000000 304clk_domain=system.clk_domain 305conf_table_reported=true |
| 306default_p_state=UNDEFINED |
|
| 271eventq_index=0 272in_addr_map=true 273latency=30000 274latency_var=0 275null=false | 307eventq_index=0 308in_addr_map=true 309latency=30000 310latency_var=0 311null=false |
| 312p_state_clk_gate_bins=20 313p_state_clk_gate_max=1000000000000 314p_state_clk_gate_min=1000 315power_model=Null |
|
| 276range=0:134217727 277port=system.membus.master[0] 278 279[system.voltage_domain] 280type=VoltageDomain 281eventq_index=0 282voltage=1.000000 283 | 316range=0:134217727 317port=system.membus.master[0] 318 319[system.voltage_domain] 320type=VoltageDomain 321eventq_index=0 322voltage=1.000000 323 |